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-rw-r--r--platform/wavelet3d/GenW3DHost.scala2
-rw-r--r--platform/wavelet3d/w3d_host_vexriscv.v4
-rw-r--r--platform/wavelet3d/w3d_interconnect.sv14
-rw-r--r--rtl/gfx/gfx_top.sv4
-rw-r--r--rtl/gfx/gfx_xbar_sched.sv95
-rw-r--r--rtl/gfx/gfx_xbar_vram.sv39
-rw-r--r--target/w3d_de1soc/w3d_de1soc.sv116
7 files changed, 149 insertions, 125 deletions
diff --git a/platform/wavelet3d/GenW3DHost.scala b/platform/wavelet3d/GenW3DHost.scala
index 3aa181a..a6c78ec 100644
--- a/platform/wavelet3d/GenW3DHost.scala
+++ b/platform/wavelet3d/GenW3DHost.scala
@@ -59,7 +59,7 @@ object GenW3DHost extends App{
)
),
new StaticMemoryTranslatorPlugin(
- ioRange = _(31 downto 27) > 0x0
+ ioRange = _(31 downto 26) >= 0x7 // Inicia en 0x1c000000 (0x3c000000 para HPS)
),
new DecoderSimplePlugin(
catchIllegalInstruction = true
diff --git a/platform/wavelet3d/w3d_host_vexriscv.v b/platform/wavelet3d/w3d_host_vexriscv.v
index 4ae9e2c..b46c702 100644
--- a/platform/wavelet3d/w3d_host_vexriscv.v
+++ b/platform/wavelet3d/w3d_host_vexriscv.v
@@ -5451,7 +5451,7 @@ module w3d_host_vexriscv (
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
- assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (5'h00 < IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 27]);
+ assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (6'h07 <= IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 26]);
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
@@ -5460,7 +5460,7 @@ module w3d_host_vexriscv (
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
- assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (5'h00 < DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 27]);
+ assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (6'h07 <= DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 26]);
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
diff --git a/platform/wavelet3d/w3d_interconnect.sv b/platform/wavelet3d/w3d_interconnect.sv
index 17d7522..22dd5ee 100644
--- a/platform/wavelet3d/w3d_interconnect.sv
+++ b/platform/wavelet3d/w3d_interconnect.sv
@@ -58,11 +58,15 @@ module w3d_interconnect_dram
if_axib.m dram
);
- defparam xbar.NM = 3;
- defparam xbar.NS = 1;
- defparam xbar.OPT_LOWPOWER = 0;
+ // VRAM es 0x1c000000..0x1fffffff
+ function logic[31:0] vram_addr(logic[31:0] addr);
+ return {6'b000111, addr[25:0]};
+ endfunction
defparam
+ xbar.NM = 3,
+ xbar.NS = 1,
+ xbar.OPT_LOWPOWER = 0,
xbar.SLAVE_ADDR = '0,
xbar.SLAVE_MASK = '0,
xbar.C_AXI_ID_WIDTH = 8;
@@ -88,7 +92,7 @@ module w3d_interconnect_dram
host_ibus.awid
}),
.S_AXI_AWADDR({
- gfx_vram.awaddr,
+ vram_addr(gfx_vram.awaddr),
host_dbus.awaddr,
host_ibus.awaddr
}),
@@ -175,7 +179,7 @@ module w3d_interconnect_dram
host_ibus.arid
}),
.S_AXI_ARADDR({
- gfx_vram.araddr,
+ vram_addr(gfx_vram.araddr),
host_dbus.araddr,
host_ibus.araddr
}),
diff --git a/rtl/gfx/gfx_top.sv b/rtl/gfx/gfx_top.sv
index 99f2133..93d5585 100644
--- a/rtl/gfx/gfx_top.sv
+++ b/rtl/gfx/gfx_top.sv
@@ -10,7 +10,7 @@ import gfx::*;
if_axil.s host_ctrl
);
- if_axib data_mem(), insn_mem();
+ if_axib data_mem(), insn_mem(), sched_vram();
if_axil bootrom_axi(), debug_axi(), host_ctrl_axi(), sched_axi(), shader_0_axi();
logic irq_host_ctrl;
@@ -64,6 +64,7 @@ import gfx::*;
.sched(sched_axi.s),
+ .vram(sched_vram.m),
.debug(debug_axi.m),
.bootrom(bootrom_axi.m),
.shader_0(shader_0_axi.m),
@@ -75,6 +76,7 @@ import gfx::*;
.clk,
.srst_n,
.vram,
+ .sched(sched_vram.s),
.shader_0_data(data_mem.s),
.shader_0_insn(insn_mem.s)
);
diff --git a/rtl/gfx/gfx_xbar_sched.sv b/rtl/gfx/gfx_xbar_sched.sv
index 32305cd..f0aef84 100644
--- a/rtl/gfx/gfx_xbar_sched.sv
+++ b/rtl/gfx/gfx_xbar_sched.sv
@@ -6,12 +6,16 @@ import gfx::*;
if_axil.s sched,
+ if_axib.m vram,
+
if_axil.m debug,
bootrom,
shader_0,
host_ctrl
);
+ if_axil vram_lite();
+
localparam word
BOOTROM_MASK = 32'hfff0_0000,
DEBUG_BASE = 32'h0020_0000,
@@ -19,13 +23,16 @@ import gfx::*;
HOST_CTRL_BASE = 32'h0030_0000,
HOST_CTRL_MASK = 32'hfff0_0000,
SHADER_0_BASE = 32'h0100_0000,
- SHADER_0_MASK = 32'hfff0_0000;
+ SHADER_0_MASK = 32'hfff0_0000,
+ VRAM_BASE = 32'h1c00_0000,
+ VRAM_MASK = 32'hfc00_0000;
defparam xbar.NM = 1;
- defparam xbar.NS = 4;
+ defparam xbar.NS = 5;
defparam xbar.OPT_LOWPOWER = 0;
defparam xbar.SLAVE_ADDR = {
+ VRAM_BASE,
SHADER_0_BASE,
HOST_CTRL_BASE,
DEBUG_BASE,
@@ -33,6 +40,7 @@ import gfx::*;
};
defparam xbar.SLAVE_MASK = {
+ VRAM_MASK,
SHADER_0_MASK,
HOST_CTRL_MASK,
DEBUG_MASK,
@@ -69,6 +77,7 @@ import gfx::*;
.S_AXI_RRESP(),
.M_AXI_AWADDR({
+ vram_lite.m.awaddr,
shader_0.awaddr,
host_ctrl.awaddr,
debug.awaddr,
@@ -76,12 +85,14 @@ import gfx::*;
}),
.M_AXI_AWPROT(),
.M_AXI_AWVALID({
+ vram_lite.m.awvalid,
shader_0.awvalid,
host_ctrl.awvalid,
debug.awvalid,
bootrom.awvalid
}),
.M_AXI_AWREADY({
+ vram_lite.m.awready,
shader_0.awready,
host_ctrl.awready,
debug.awready,
@@ -89,6 +100,7 @@ import gfx::*;
}),
.M_AXI_WDATA({
+ vram_lite.m.wdata,
shader_0.wdata,
host_ctrl.wdata,
debug.wdata,
@@ -96,12 +108,14 @@ import gfx::*;
}),
.M_AXI_WSTRB(),
.M_AXI_WVALID({
+ vram_lite.m.wvalid,
shader_0.wvalid,
host_ctrl.wvalid,
debug.wvalid,
bootrom.wvalid
}),
.M_AXI_WREADY({
+ vram_lite.m.wready,
shader_0.wready,
host_ctrl.wready,
debug.wready,
@@ -110,12 +124,14 @@ import gfx::*;
.M_AXI_BRESP('0),
.M_AXI_BVALID({
+ vram_lite.m.bvalid,
shader_0.bvalid,
host_ctrl.bvalid,
debug.bvalid,
bootrom.bvalid
}),
.M_AXI_BREADY({
+ vram_lite.m.bready,
shader_0.bready,
host_ctrl.bready,
debug.bready,
@@ -123,6 +139,7 @@ import gfx::*;
}),
.M_AXI_ARADDR({
+ vram_lite.m.araddr,
shader_0.araddr,
host_ctrl.araddr,
debug.araddr,
@@ -130,12 +147,14 @@ import gfx::*;
}),
.M_AXI_ARPROT(),
.M_AXI_ARVALID({
+ vram_lite.m.arvalid,
shader_0.arvalid,
host_ctrl.arvalid,
debug.arvalid,
bootrom.arvalid
}),
.M_AXI_ARREADY({
+ vram_lite.m.arready,
shader_0.arready,
host_ctrl.arready,
debug.arready,
@@ -143,6 +162,7 @@ import gfx::*;
}),
.M_AXI_RDATA({
+ vram_lite.m.rdata,
shader_0.rdata,
host_ctrl.rdata,
debug.rdata,
@@ -150,12 +170,14 @@ import gfx::*;
}),
.M_AXI_RRESP('0),
.M_AXI_RVALID({
+ vram_lite.m.rvalid,
shader_0.rvalid,
host_ctrl.rvalid,
debug.rvalid,
bootrom.rvalid
}),
.M_AXI_RREADY({
+ vram_lite.m.rready,
shader_0.rready,
host_ctrl.rready,
debug.rready,
@@ -163,4 +185,73 @@ import gfx::*;
})
);
+ defparam
+ vram_bridge.C_AXI_ID_WIDTH = 8,
+ vram_bridge.C_AXI_ADDR_WIDTH = 32,
+ vram_bridge.C_AXI_DATA_WIDTH = 32;
+
+ axilite2axi vram_bridge
+ (
+ .ACLK(clk),
+ .ARESETN(srst_n),
+
+ .S_AXI_AWVALID(vram_lite.s.awvalid),
+ .S_AXI_AWREADY(vram_lite.s.awready),
+ .S_AXI_AWADDR(vram_lite.s.awaddr),
+ .S_AXI_AWPROT(3'b0),
+ .S_AXI_WVALID(vram_lite.s.wvalid),
+ .S_AXI_WREADY(vram_lite.s.wready),
+ .S_AXI_WDATA(vram_lite.s.wdata),
+ .S_AXI_WSTRB(4'b1111),
+ .S_AXI_BVALID(vram_lite.s.bvalid),
+ .S_AXI_BREADY(vram_lite.s.bready),
+ .S_AXI_BRESP(),
+ .S_AXI_ARVALID(vram_lite.s.arvalid),
+ .S_AXI_ARREADY(vram_lite.s.arready),
+ .S_AXI_ARADDR(vram_lite.s.araddr),
+ .S_AXI_ARPROT(3'b0),
+ .S_AXI_RVALID(vram_lite.s.rvalid),
+ .S_AXI_RREADY(vram_lite.s.rready),
+ .S_AXI_RDATA(vram_lite.s.rdata),
+ .S_AXI_RRESP(),
+
+ .M_AXI_AWVALID(vram.awvalid),
+ .M_AXI_AWREADY(vram.awready),
+ .M_AXI_AWID(vram.awid),
+ .M_AXI_AWADDR(vram.awaddr),
+ .M_AXI_AWLEN(vram.awlen),
+ .M_AXI_AWSIZE(vram.awsize),
+ .M_AXI_AWBURST(vram.awburst),
+ .M_AXI_AWLOCK(),
+ .M_AXI_AWCACHE(),
+ .M_AXI_AWPROT(),
+ .M_AXI_AWQOS(),
+ .M_AXI_WVALID(vram.wvalid),
+ .M_AXI_WREADY(vram.wready),
+ .M_AXI_WDATA(vram.wdata),
+ .M_AXI_WSTRB(vram.wstrb),
+ .M_AXI_WLAST(vram.wlast),
+ .M_AXI_BVALID(vram.bvalid),
+ .M_AXI_BREADY(vram.bready),
+ .M_AXI_BID(vram.bid),
+ .M_AXI_BRESP(vram.bresp),
+ .M_AXI_ARVALID(vram.arvalid),
+ .M_AXI_ARREADY(vram.arready),
+ .M_AXI_ARID(vram.arid),
+ .M_AXI_ARADDR(vram.araddr),
+ .M_AXI_ARLEN(vram.arlen),
+ .M_AXI_ARSIZE(vram.arsize),
+ .M_AXI_ARBURST(vram.arburst),
+ .M_AXI_ARLOCK(),
+ .M_AXI_ARCACHE(),
+ .M_AXI_ARPROT(),
+ .M_AXI_ARQOS(),
+ .M_AXI_RVALID(vram.rvalid),
+ .M_AXI_RREADY(vram.rready),
+ .M_AXI_RID(vram.rid),
+ .M_AXI_RDATA(vram.rdata),
+ .M_AXI_RLAST(vram.rlast),
+ .M_AXI_RRESP(vram.rresp)
+ );
+
endmodule
diff --git a/rtl/gfx/gfx_xbar_vram.sv b/rtl/gfx/gfx_xbar_vram.sv
index 3ce8425..c643948 100644
--- a/rtl/gfx/gfx_xbar_vram.sv
+++ b/rtl/gfx/gfx_xbar_vram.sv
@@ -3,17 +3,17 @@ module gfx_xbar_vram
input logic clk,
srst_n,
- if_axib.s shader_0_data,
+ if_axib.s sched,
+ shader_0_data,
shader_0_insn,
if_axib.m vram
);
- defparam xbar.NM = 2;
- defparam xbar.NS = 1;
- defparam xbar.OPT_LOWPOWER = 0;
-
defparam
+ xbar.NM = 3,
+ xbar.NS = 1,
+ xbar.OPT_LOWPOWER = 0,
xbar.SLAVE_ADDR = '0,
xbar.SLAVE_MASK = '0,
xbar.C_AXI_ID_WIDTH = 8;
@@ -24,30 +24,37 @@ module gfx_xbar_vram
.S_AXI_ARESETN(srst_n),
.S_AXI_AWVALID({
+ sched.awvalid,
shader_0_data.awvalid,
shader_0_insn.awvalid
}),
.S_AXI_AWREADY({
+ sched.awready,
shader_0_data.awready,
shader_0_insn.awready
}),
.S_AXI_AWID({
+ sched.awid,
shader_0_data.awid,
shader_0_insn.awid
}),
.S_AXI_AWADDR({
+ sched.awaddr,
shader_0_data.awaddr,
shader_0_insn.awaddr
}),
.S_AXI_AWLEN({
+ sched.awlen,
shader_0_data.awlen,
shader_0_insn.awlen
}),
.S_AXI_AWSIZE({
+ sched.awsize,
shader_0_data.awsize,
shader_0_insn.awsize
}),
.S_AXI_AWBURST({
+ sched.awburst,
shader_0_data.awburst,
shader_0_insn.awburst
}),
@@ -57,68 +64,84 @@ module gfx_xbar_vram
.S_AXI_AWQOS('0),
.S_AXI_WVALID({
+ sched.wvalid,
shader_0_data.wvalid,
shader_0_insn.wvalid
}),
.S_AXI_WREADY({
+ sched.wready,
shader_0_data.wready,
shader_0_insn.wready
}),
.S_AXI_WDATA({
+ sched.wdata,
shader_0_data.wdata,
shader_0_insn.wdata
}),
.S_AXI_WSTRB({
+ sched.wstrb,
shader_0_data.wstrb,
shader_0_insn.wstrb
}),
.S_AXI_WLAST({
+ sched.wlast,
shader_0_data.wlast,
shader_0_insn.wlast
}),
.S_AXI_BVALID({
+ sched.bvalid,
shader_0_data.bvalid,
shader_0_insn.bvalid
}),
.S_AXI_BREADY({
+ sched.bready,
shader_0_data.bready,
shader_0_insn.bready
}),
.S_AXI_BID({
+ sched.bid,
shader_0_data.bid,
shader_0_insn.bid
}),
.S_AXI_BRESP({
+ sched.bresp,
shader_0_data.bresp,
shader_0_insn.bresp
}),
.S_AXI_ARVALID({
+ sched.arvalid,
shader_0_data.arvalid,
shader_0_insn.arvalid
}),
.S_AXI_ARREADY({
+ sched.arready,
shader_0_data.arready,
shader_0_insn.arready
}),
.S_AXI_ARID({
+ sched.arid,
shader_0_data.arid,
shader_0_insn.arid
}),
.S_AXI_ARADDR({
+ sched.araddr,
shader_0_data.araddr,
shader_0_insn.araddr
}),
.S_AXI_ARLEN({
+ sched.arlen,
shader_0_data.arlen,
shader_0_insn.arlen
}),
.S_AXI_ARSIZE({
+ sched.arsize,
shader_0_data.arsize,
shader_0_insn.arsize
}),
.S_AXI_ARBURST({
+ sched.arburst,
shader_0_data.arburst,
shader_0_insn.arburst
}),
@@ -128,26 +151,32 @@ module gfx_xbar_vram
.S_AXI_ARQOS('0),
.S_AXI_RVALID({
+ sched.rvalid,
shader_0_data.rvalid,
shader_0_insn.rvalid
}),
.S_AXI_RREADY({
+ sched.rready,
shader_0_data.rready,
shader_0_insn.rready
}),
.S_AXI_RID({
+ sched.rid,
shader_0_data.rid,
shader_0_insn.rid
}),
.S_AXI_RDATA({
+ sched.rdata,
shader_0_data.rdata,
shader_0_insn.rdata
}),
.S_AXI_RRESP({
+ sched.rresp,
shader_0_data.rresp,
shader_0_insn.rresp
}),
.S_AXI_RLAST({
+ sched.rlast,
shader_0_data.rlast,
shader_0_insn.rlast
}),
diff --git a/target/w3d_de1soc/w3d_de1soc.sv b/target/w3d_de1soc/w3d_de1soc.sv
index 65d0f4c..1d188fd 100644
--- a/target/w3d_de1soc/w3d_de1soc.sv
+++ b/target/w3d_de1soc/w3d_de1soc.sv
@@ -32,6 +32,11 @@ module w3d_de1soc
output wire [7:0] vga_dac_b
);
+ // Sistema ve 512MiB superior (0x20000000-0x3fffffff) de SDRAM de HPS
+ function logic[31:0] f2s_addr(logic[31:0] addr);
+ return {3'b001, addr[28:0]};
+ endfunction
+
logic button, reset_reset_n, sys_clk, sys_rst_n, sys_srst_n;
logic dram_arready, dram_arvalid, dram_awready, dram_awvalid, dram_bready, dram_bvalid,
@@ -62,20 +67,6 @@ module w3d_de1soc
logic[3:0] mmio_wstrb;
logic[31:0] mmio_araddr, mmio_awaddr, mmio_rdata, mmio_wdata;
- /*logic dram_axi3_arready, dram_axi3_arvalid, dram_axi3_awready, dram_axi3_awvalid,
- dram_axi3_bready, dram_axi3_bvalid, dram_axi3_rlast, dram_axi3_rready,
- dram_axi3_rvalid, dram_axi3_wlast, dram_axi3_wready, dram_axi3_wvalid;
-
- logic[1:0] dram_axi3_arburst, dram_axi3_arlock, dram_axi3_awburst, dram_axi3_awlock,
- dram_axi3_bresp, dram_axi3_rresp;
-
- logic[3:0] dram_axi3_arcache, dram_axi3_arlen, ram_axi3_awcache, dram_axi3_awlen,
- dram_axi3_wstrb;
-
- logic[2:0] dram_axi3_arprot, dram_axi3_arsize, dram_axi3_awprot, dram_axi3_awsize;
- logic[7:0] dram_axi3_arid, dram_axi3_awid, dram_axi3_bid, dram_axi3_rid, dram_axi3_wid;
- logic[31:0] dram_axi3_araddr, dram_axi3_awaddr, dram_axi3_rdata, dram_axi3_wdata;*/
-
logic mmio_full_arlock, mmio_full_awlock;
logic[2:0] mmio_full_arprot, mmio_full_awprot;
logic[3:0] mmio_full_arcache, mmio_full_awcache;
@@ -127,13 +118,13 @@ module w3d_de1soc
.vga_dac_R(vga_dac_r),
.vga_dac_G(vga_dac_g),
.vga_dac_B(vga_dac_b),
- .dram_axi_bridge_s0_araddr(dram_araddr),
+ .dram_axi_bridge_s0_araddr(f2s_addr(dram_araddr)),
.dram_axi_bridge_s0_arlen(dram_arlen),
.dram_axi_bridge_s0_arid(dram_arid),
.dram_axi_bridge_s0_arsize(dram_arsize),
.dram_axi_bridge_s0_arburst(dram_arburst),
.dram_axi_bridge_s0_arvalid(dram_arvalid),
- .dram_axi_bridge_s0_awaddr(dram_awaddr),
+ .dram_axi_bridge_s0_awaddr(f2s_addr(dram_awaddr)),
.dram_axi_bridge_s0_awlen(dram_awlen),
.dram_axi_bridge_s0_awid(dram_awid),
.dram_axi_bridge_s0_awsize(dram_awsize),
@@ -264,99 +255,6 @@ module w3d_de1soc
.jtag_tdo()
);
- /*defparam
- dram_bridge.C_AXI_ID_WIDTH = 8,
- dram_bridge.C_AXI_ADDR_WIDTH = 32,
- dram_bridge.C_AXI_DATA_WIDTH = 32;
-
- axi2axi3 dram_bridge
- (
- .S_AXI_ACLK(sys_clk),
- .S_AXI_ARESETN(sys_srst_n),
-
- .S_AXI_AWVALID(dram_awvalid),
- .S_AXI_AWREADY(dram_awready),
- .S_AXI_AWID(dram_awid),
- .S_AXI_AWADDR(dram_awaddr),
- .S_AXI_AWLEN(dram_awlen),
- .S_AXI_AWSIZE(dram_awsize),
- .S_AXI_AWBURST(dram_awburst),
- .S_AXI_AWLOCK(0),
- .S_AXI_AWCACHE(4'b0011), // Normal non-cacheable, non-bufferable
- .S_AXI_AWPROT(3'b0),
- .S_AXI_AWQOS(4'b0),
-
- .S_AXI_WVALID(dram_wvalid),
- .S_AXI_WREADY(dram_wready),
- .S_AXI_WDATA(dram_wdata),
- .S_AXI_WSTRB(dram_wstrb),
- .S_AXI_WLAST(dram_wlast),
-
- .S_AXI_BVALID(dram_bvalid),
- .S_AXI_BREADY(dram_bready),
- .S_AXI_BID(dram_bid),
- .S_AXI_BRESP(dram_bresp),
-
- .S_AXI_ARVALID(dram_arvalid),
- .S_AXI_ARREADY(dram_arready),
- .S_AXI_ARID(dram_arid),
- .S_AXI_ARADDR(dram_araddr),
- .S_AXI_ARLEN(dram_arlen),
- .S_AXI_ARSIZE(dram_arsize),
- .S_AXI_ARBURST(dram_arburst),
- .S_AXI_ARLOCK(0),
- .S_AXI_ARCACHE(4'b0011), // Normal non-cacheable, non-bufferable
- .S_AXI_ARPROT(3'b0),
- .S_AXI_ARQOS(4'b0),
-
- .S_AXI_RVALID(dram_rvalid),
- .S_AXI_RREADY(dram_rready),
- .S_AXI_RID(dram_rid),
- .S_AXI_RDATA(dram_rdata),
- .S_AXI_RLAST(dram_rlast),
- .S_AXI_RRESP(dram_rresp),
-
- .M_AXI_AWVALID(dram_axi3_awvalid),
- .M_AXI_AWREADY(dram_axi3_awready),
- .M_AXI_AWID(dram_axi3_awid),
- .M_AXI_AWADDR(dram_axi3_awaddr),
- .M_AXI_AWLEN(dram_axi3_awlen),
- .M_AXI_AWSIZE(dram_axi3_awsize),
- .M_AXI_AWBURST(dram_axi3_awburst),
- .M_AXI_AWLOCK(dram_axi3_awlock),
- .M_AXI_AWCACHE(dram_axi3_awcache),
- .M_AXI_AWPROT(dram_axi3_awprot),
- .M_AXI_AWQOS(),
-
- .M_AXI_WVALID(dram_axi3_wvalid),
- .M_AXI_WREADY(dram_axi3_wready),
- .M_AXI_WID(dram_axi3_wid),
- .M_AXI_WDATA(dram_axi3_wdata),
- .M_AXI_WSTRB(dram_axi3_wstrb),
- .M_AXI_WLAST(dram_axi3_wlast),
- .M_AXI_BVALID(dram_axi3_bvalid),
- .M_AXI_BREADY(dram_axi3_bready),
- .M_AXI_BID(dram_axi3_bid),
- .M_AXI_BRESP(dram_axi3_bresp),
- .M_AXI_ARVALID(dram_axi3_arvalid),
- .M_AXI_ARREADY(dram_axi3_arready),
- .M_AXI_ARID(dram_axi3_arid),
- .M_AXI_ARADDR(dram_axi3_araddr),
- .M_AXI_ARLEN(dram_axi3_arlen),
- .M_AXI_ARSIZE(dram_axi3_arsize),
- .M_AXI_ARBURST(dram_axi3_arburst),
- .M_AXI_ARLOCK(dram_axi3_arlock),
- .M_AXI_ARCACHE(dram_axi3_arcache),
- .M_AXI_ARPROT(dram_axi3_arprot),
- .M_AXI_ARQOS(),
- .M_AXI_RVALID(dram_axi3_rvalid),
- .M_AXI_RREADY(dram_axi3_rready),
- .M_AXI_RID(dram_axi3_rid),
- .M_AXI_RDATA(dram_axi3_rdata),
- .M_AXI_RLAST(dram_axi3_rlast),
- .M_AXI_RRESP(dram_axi3_rresp)
- );*/
-
defparam
mmio_bridge.C_AXI_ID_WIDTH = 8,
mmio_bridge.C_AXI_ADDR_WIDTH = 32,
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 05:20:22 +0000