diff options
Diffstat (limited to 'rtl/core/control/control.sv')
| -rw-r--r-- | rtl/core/control/control.sv | 41 |
1 files changed, 7 insertions, 34 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 5f7de3a..2c5c6f1 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -43,8 +43,6 @@ module core_control mem_write ); - ctrl_cycle cycle, next_cycle; - logic final_writeback, final_update_flags, ldst, ldst_pre, ldst_increment, ldst_writeback, pop_valid, data_snd_is_imm, data_snd_shift_by_reg, trivial_shift, @@ -67,6 +65,13 @@ module core_control assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00}; assign next_pc_visible = fetch_insn_pc + 2; + ctrl_cycle cycle, next_cycle; + + core_control_cycles cycles + ( + .* + ); + logic bubble, next_bubble; core_control_stall ctrl_stall @@ -90,35 +95,6 @@ module core_control default: shifter_shift = {2'b00, data_shift_imm}; endcase - next_cycle = ISSUE; - - unique case(cycle) - ISSUE: - if(exception) - next_cycle = EXCEPTION; - else if(data_snd_shift_by_reg) - next_cycle = RD_INDIRECT_SHIFT; - else if(~trivial_shift) - next_cycle = WITH_SHIFT; - - RD_INDIRECT_SHIFT: - if(~trivial_shift) - next_cycle = WITH_SHIFT; - - TRANSFER: - if(!mem_ready || pop_valid) - next_cycle = TRANSFER; - else if(ldst_writeback) - next_cycle = BASE_WRITEBACK; - - default: ; - endcase - - if(bubble) - next_cycle = ISSUE; - else if(next_cycle == ISSUE && ldst) - next_cycle = TRANSFER; - unique case(cycle) TRANSFER: alu_a = saved_base; EXCEPTION: alu_a = {pc, 2'b00}; @@ -143,7 +119,6 @@ module core_control end always_ff @(posedge clk) begin - cycle <= next_cycle; branch <= 0; writeback <= 0; update_flags <= 0; @@ -271,8 +246,6 @@ module core_control end initial begin - cycle = ISSUE; - pc = 0; pc_visible = 2; |