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-rw-r--r--rtl/core/control/control.sv13
1 files changed, 6 insertions, 7 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index d214525..49c1e8b 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -105,6 +105,11 @@ module core_control
.*
);
+ core_control_data ctrl_mul
+ (
+ .*
+ );
+
logic final_writeback, final_update_flags;
reg_num final_rd;
@@ -126,14 +131,8 @@ module core_control
unique0 case(next_cycle)
ISSUE:
- if(issue) begin
- mul <= dec.mul;
- mul_add <= dec_mul.add;
- mul_long <= dec_mul.long_mul;
- mul_signed <= dec_mul.signed_mul;
-
+ if(issue)
coproc <= dec.coproc;
- end
endcase
end