diff options
| -rw-r--r-- | conspiracion.qsf | 1 | ||||
| -rw-r--r-- | rtl/core/control/control.sv | 13 | ||||
| -rw-r--r-- | rtl/core/control/mul.sv | 35 |
3 files changed, 42 insertions, 7 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index 77c8556..a9e7fc3 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -142,6 +142,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/cycles.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/data.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/exception.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/issue.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/mul.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/ldst.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/pop.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/select.sv diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index d214525..49c1e8b 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -105,6 +105,11 @@ module core_control .* ); + core_control_data ctrl_mul + ( + .* + ); + logic final_writeback, final_update_flags; reg_num final_rd; @@ -126,14 +131,8 @@ module core_control unique0 case(next_cycle) ISSUE: - if(issue) begin - mul <= dec.mul; - mul_add <= dec_mul.add; - mul_long <= dec_mul.long_mul; - mul_signed <= dec_mul.signed_mul; - + if(issue) coproc <= dec.coproc; - end endcase end diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv new file mode 100644 index 0000000..8d23514 --- /dev/null +++ b/rtl/core/control/mul.sv @@ -0,0 +1,35 @@ +`include "core/uarch.sv" + +module core_control_mul +( + input logic clk, + + input datapath_decode dec, + input mul_decode dec_mul, + input logic mul_ready, + + input ctrl_cycle next_cycle, + input logic issue, + + output logic mul, + mul_add, + mul_long, + mul_signed +); + + always_ff @(posedge clk) + if(next_cycle == ISSUE && issue) begin + mul <= dec.mul; + mul_add <= dec_mul.add; + mul_long <= dec_mul.long_mul; + mul_signed <= dec_mul.signed_mul; + end + + initial begin + mul = 0; + mul_add = 0; + mul_long = 0; + mul_signed = 0; + end + +endmodule |