diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-05-16 01:08:04 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-24 05:58:19 -0600 |
| commit | b21c321a059e11edeece1c90d97776bb0716d7a0 (patch) | |
| tree | cb7c3e6c2a5f6fd153c3b01d61040a2c901e0ba8 /rtl/wb2axip/easyaxil.v | |
| parent | a6c23ba92d0c2cad9862de1cb11c19b4e06fc0e6 (diff) | |
rtl: fix quartus errors: parser, synthesis, fitter
Diffstat (limited to 'rtl/wb2axip/easyaxil.v')
| -rw-r--r-- | rtl/wb2axip/easyaxil.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/wb2axip/easyaxil.v b/rtl/wb2axip/easyaxil.v index 0c88b11..e96db11 100644 --- a/rtl/wb2axip/easyaxil.v +++ b/rtl/wb2axip/easyaxil.v @@ -40,7 +40,7 @@ // //////////////////////////////////////////////////////////////////////////////// // -`default_nettype none +//`default_nettype none // }}} module easyaxil #( // {{{ @@ -49,7 +49,7 @@ module easyaxil #( // is fixed at a width of 32-bits by Xilinx def'n, and 2) since // we only ever have 4 configuration words. parameter C_AXI_ADDR_WIDTH = 4, - localparam C_AXI_DATA_WIDTH = 32, + /*local*/parameter C_AXI_DATA_WIDTH = 32, parameter [0:0] OPT_SKIDBUFFER = 1'b0, parameter [0:0] OPT_LOWPOWER = 0 // }}} |