From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Thu, 16 May 2024 01:08:04 -0600 Subject: rtl: fix quartus errors: parser, synthesis, fitter --- rtl/wb2axip/easyaxil.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'rtl/wb2axip/easyaxil.v') diff --git a/rtl/wb2axip/easyaxil.v b/rtl/wb2axip/easyaxil.v index 0c88b11..e96db11 100644 --- a/rtl/wb2axip/easyaxil.v +++ b/rtl/wb2axip/easyaxil.v @@ -40,7 +40,7 @@ // //////////////////////////////////////////////////////////////////////////////// // -`default_nettype none +//`default_nettype none // }}} module easyaxil #( // {{{ @@ -49,7 +49,7 @@ module easyaxil #( // is fixed at a width of 32-bits by Xilinx def'n, and 2) since // we only ever have 4 configuration words. parameter C_AXI_ADDR_WIDTH = 4, - localparam C_AXI_DATA_WIDTH = 32, + /*local*/parameter C_AXI_DATA_WIDTH = 32, parameter [0:0] OPT_SKIDBUFFER = 1'b0, parameter [0:0] OPT_LOWPOWER = 0 // }}} -- cgit v1.2.3