diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-10-05 00:36:37 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-05 13:07:57 -0600 |
| commit | 4acd900c4602db0353d11bf6841ddadfd80c57b8 (patch) | |
| tree | fe24637ccd16fefcf25f0c8d8e65b01d19a1760c /rtl/top/hps_sdram_test.sv | |
| parent | d173727c1ed34652613fc046d522a43ac9ef015e (diff) | |
Makefile, tb: add support for cocotb
Diffstat (limited to 'rtl/top/hps_sdram_test.sv')
| -rw-r--r-- | rtl/top/hps_sdram_test.sv | 93 |
1 files changed, 0 insertions, 93 deletions
diff --git a/rtl/top/hps_sdram_test.sv b/rtl/top/hps_sdram_test.sv deleted file mode 100644 index 28d6175..0000000 --- a/rtl/top/hps_sdram_test.sv +++ /dev/null @@ -1,93 +0,0 @@ -module hps_sdram_test -( - input wire clk_clk, - output wire [12:0] memory_mem_a, - output wire [2:0] memory_mem_ba, - output wire memory_mem_ck, - output wire memory_mem_ck_n, - output wire memory_mem_cke, - output wire memory_mem_cs_n, - output wire memory_mem_ras_n, - output wire memory_mem_cas_n, - output wire memory_mem_we_n, - output wire memory_mem_reset_n, - inout wire [7:0] memory_mem_dq, - inout wire memory_mem_dqs, - inout wire memory_mem_dqs_n, - output wire memory_mem_odt, - output wire memory_mem_dm, - input wire memory_oct_rzqin, - /*input wire reset_reset_n,*/ - - input logic dir, clr, mov, add, io, - output logic[7:0] out, - output logic done -); - - wire reset_reset_n; - assign reset_reset_n = 1'b1; - - enum { - IDLE, - IO, - RELEASE - } state; - - logic[29:0] addr; - logic[31:0] data_rd, data_wr; - logic ready, write, start; - - logic [7:0] leds; - - platform plat - ( - .master_0_core_addr(addr), - .master_0_core_data_rd(data_rd), - .master_0_core_data_wr(data_wr), - .master_0_core_ready(ready), - .master_0_core_write(write), - .master_0_core_start(start), - .* - ); - - initial begin - addr = 0; - start = 0; - state = IDLE; - done = 0; - end - - assign data_wr[7:0] = out; - assign write = dir; - - always_ff @(posedge clk_clk) unique case(state) - IDLE: begin - state <= RELEASE; - - if(~clr) - out <= 0; - else if(~mov) - addr <= dir ? addr + 1 : addr - 1; - else if(~add) - out <= dir ? out + 1 : out - 1; - else if(~io) begin - start <= 1; - state <= IO; - end - end - - IO: begin - done <= 1; - start <= 0; - if(ready) begin - if(~dir) out <= data_rd[7:0]; - state <= RELEASE; - end - end - - RELEASE: begin - done <= ~io; - if(clr & mov & add & io) state <= IDLE; - end - endcase -endmodule |
