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-rw-r--r--.gitignore2
-rw-r--r--Makefile68
-rw-r--r--flake.nix9
-rw-r--r--rtl/top/decode_test.sv14
-rw-r--r--rtl/top/fetch_test.sv25
-rw-r--r--rtl/top/hps_sdram_test.sv93
-rw-r--r--rtl/top/mul_test.sv33
-rw-r--r--rtl/top/smp_sim.sv35
-rw-r--r--tb/__init__.py0
-rw-r--r--tb/top/__init__.py0
-rw-r--r--tb/top/conspiracion.cpp84
-rw-r--r--tb/top/conspiracion/args.hxx (renamed from tb/args.hxx)0
-rw-r--r--tb/top/conspiracion/platform.sv (renamed from tb/platform.sv)0
-rw-r--r--tb/top/conspiracion/sim_slave.cpp (renamed from tb/sim_slave.cpp)0
-rw-r--r--tb/top/conspiracion/sim_slave.hpp (renamed from tb/sim_slave.hpp)4
-rw-r--r--tb/top/conspiracion/sim_slave.sv (renamed from tb/sim_slave.sv)0
-rw-r--r--tb/top/conspiracion/vga_domain.sv (renamed from tb/vga_domain.sv)0
-rw-r--r--tb/top/decode_test.cpp101
-rw-r--r--tb/top/fetch_test.cpp166
-rw-r--r--tb/top/hps_sdram_test.cpp93
-rw-r--r--tb/top/mul_test.cpp71
-rw-r--r--tb/top/smp_sim.cpp0
-rw-r--r--tb/top/smp_sim.py0
23 files changed, 139 insertions, 659 deletions
diff --git a/.gitignore b/.gitignore
index f6bb125..0a1c985 100644
--- a/.gitignore
+++ b/.gitignore
@@ -46,6 +46,8 @@ hps_isw_handoff/
*~
*.vcd
*.fst
+*.dat
+*.xml
qmegawiz_errors_log.txt
cr_ie_info.json
u-boot
diff --git a/Makefile b/Makefile
index e2bdbe9..813990c 100644
--- a/Makefile
+++ b/Makefile
@@ -13,6 +13,7 @@ DEMO_OBJ_DIR := $(OBJ_DIR)/$(TOP)/demo
DIST_OBJ_DIR := $(OBJ_DIR)/$(TOP)/dist
RBF_OUT_DIR := output_files
VERILATOR ?= verilator
+COCOTB_CONFIG ?= cocotb-config
GENHTML ?= genhtml
COCOTB_CONFIG ?= cocotb-config
CROSS_CC := $(CROSS_COMPILE)gcc
@@ -20,6 +21,14 @@ CROSS_OBJCOPY := $(CROSS_COMPILE)objcopy
CROSS_CFLAGS := -O3 -Wall -Wextra -Werror
CROSS_LDFLAGS :=
+ifeq ($(shell which $(VERILATOR)),)
+ $(error verilator not found)
+endif
+
+ifeq ($(shell which $(COCOTB_CONFIG)),)
+ $(error cocotb not found)
+endif
+
ifdef FASTER_IS_BETTER
DISABLE_COV := 1
DISABLE_RAND := 1
@@ -29,6 +38,8 @@ ifdef FASTER_IS_BETTER
LDFLAGS += -O3 -flto
endif
+CXXFLAGS += -iquote $(shell pwd)/$(TB_DIR)
+
export CXXFLAGS LDFLAGS
X_MODE := $(if $(DISABLE_RAND),fast,unique)
@@ -41,11 +52,23 @@ VFLAGS ?= \
$(if $(DISABLE_TRACE),,--trace --trace-fst --trace-structs) \
$(if $(DISABLE_COV),,--coverage)
-RTL_FILES = $(shell find $(RTL_DIR)/ ! -path '$(RTL_DIR)/top/*' -type f -name '*.sv')
+VFLAGS += -O3 --cc --exe -y $(RTL_DIR) --prefix Vtop
+
+LIBPYTHON = $(shell $(COCOTB_CONFIG) --libpython)
+
+COCOTB_LDFLAGS := $(LDFLAGS) \
+ -Wl,-rpath,$(shell $(COCOTB_CONFIG) --lib-dir) \
+ -L$(shell $(COCOTB_CONFIG) -config --lib-dir) \
+ -Wl,-rpath,$(dir $(LIBPYTHON)) \
+ -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils
+
+RTL_FILES := $(shell find $(RTL_DIR)/ ! -path '$(RTL_DIR)/top/*' -type f -name '*.sv')
RTL_FILES += $(shell find $(TB_DIR)/ ! -path '$(TB_DIR)/top/*' -type f -name '*.sv')
-TB_FILES = $(shell find $(TB_DIR)/ ! -path '$(TB_DIR)/top/*' -type f -name '*.cpp')
+TB_FILES := $(shell find $(TB_DIR)/ ! -path '$(TB_DIR)/top/*' -type f -name '*.cpp')
-SIMS := $(patsubst $(TB_SIM_DIR)/%.py,%,$(wildcard $(TB_SIM_DIR)/*.py))
+SIMS := \
+ $(patsubst $(TB_SIM_DIR)/%.py,%,$(wildcard $(TB_SIM_DIR)/*.py)) \
+ $(patsubst $(TB_DIR)/top/%.py,%,$(wildcard $(TB_DIR)/top/*.py))
GIT_REV := $(shell if [ -d .git ]; then echo -$$(git rev-parse --short HEAD); fi)
@@ -69,18 +92,25 @@ dist: $(if $(DISABLE_COV),,cov)
sim: $(addprefix sim/,$(SIMS))
-sim/%: $(SIM_DIR)/sim.py $(TB_SIM_DIR)/%.py exe/$(TOP) $(SIM_OBJ_DIR)/%.bin
- @$(if $(DISABLE_TRACE),,mkdir -p $(FST_DIR)/$*)
- @$< $(TB_SIM_DIR)/$*.py $(OBJ_DIR)/$(TOP)/V$(TOP) \
+sim/%: $(SIM_DIR)/sim.py $(TB_SIM_DIR)/%.py exe/$(TOP) $(SIM_OBJ_DIR)/%.bin $(FST_DIR)/%
+ @$< $(TB_SIM_DIR)/$*.py $(OBJ_DIR)/$(TOP)/Vtop \
$(SIM_OBJ_DIR)/$*.bin \
$(if $(DISABLE_COV),,--coverage $(SIM_OBJ_DIR)/$*.cov) \
$(if $(DISABLE_TRACE),,--trace $(FST_DIR)/$*/trace$(GIT_REV).fst)
+sim/%: $(TB_DIR)/top/%.py exe/% $(FST_DIR)/%
+ @LIBPYTHON_LOC=$(LIBPYTHON) MODULE=tb.top.$* \
+ $(if $(SIM_SEED),RANDOM_SEED=$(SIM_SEED)) \
+ $(OBJ_DIR)/$*/Vtop
+
+$(FST_DIR)/%:
+ @mkdir -p $@
+
vmlaunch: $(SIM_DIR)/sim.py $(SIM_DIR)/gdbstub.py exe/$(TOP)
- @ENABLE_VIDEO=1 $< $(SIM_DIR)/gdbstub.py $(OBJ_DIR)/$(TOP)/V$(TOP) build/u-boot.bin
+ @ENABLE_VIDEO=1 $< $(SIM_DIR)/gdbstub.py $(OBJ_DIR)/$(TOP)/Vtop build/u-boot.bin
demo: $(SIM_DIR)/sim.py $(SIM_DIR)/gdbstub.py exe/$(TOP) $(DEMO_OBJ_DIR)/demo.bin
- @START_HALTED=0 $< $(SIM_DIR)/gdbstub.py $(OBJ_DIR)/$(TOP)/V$(TOP) $(DEMO_OBJ_DIR)/demo.bin
+ @START_HALTED=0 $< $(SIM_DIR)/gdbstub.py $(OBJ_DIR)/$(TOP)/Vtop $(DEMO_OBJ_DIR)/demo.bin
ifndef DISABLE_COV
$(COV_DIR): $(OBJ_DIR)/$(TOP)/cov.info
@@ -130,23 +160,25 @@ $(SIM_OBJ_DIR)/%.o: $(SIM_DIR)/%.S
exe: exe/$(TOP)
-exe/%: $(OBJ_DIR)/%/V%.mk
- $(MAKE) -C $(OBJ_DIR)/$* -f V$*.mk
+exe/%: $(OBJ_DIR)/%/Vtop.mk
+ @CXXFLAGS="$(CXXFLAGS) -iquote $(shell pwd)/$(TB_DIR)/top/$*" \
+ $(MAKE) -C $(OBJ_DIR)/$* -f Vtop.mk
-.PRECIOUS: $(SIM_OBJ_DIR)/% $(SIM_OBJ_DIR)/%.o $(SIM_OBJ_DIR)/%.cov %.bin
+.PRECIOUS: $(OBJ_DIR)/%.mk $(SIM_OBJ_DIR)/% $(SIM_OBJ_DIR)/%.o $(SIM_OBJ_DIR)/%.cov %.bin
.PHONY: all clean dist demo sim
.SECONDEXPANSION:
$(OBJ_DIR)/%.mk: \
$(RTL_DIR)/top/$$(word 1,$$(subst /, ,$$*)).sv \
- $$(shell find $(RTL_DIR)/top/$$(dir $$*) -type f -name '*.sv' 2>/dev/null) \
- $$(shell find $(TB_DIR)/top/$$(dir $$*) -type f -name '*.sv' 2>/dev/null) \
+ $$(shell find $(RTL_DIR)/top/$$(dir $$*) -type f 2>/dev/null) \
$(RTL_FILES) $(TB_FILES) $(TB_DIR)/top/$$(word 1,$$(subst /, ,$$*)).cpp \
- $$(shell find $(TB_DIR)/top/$$(dir $$*) -type f -name '*.cpp' 2>/dev/null)
+ $$(shell find $(TB_DIR)/top/$$(dir $$*) -type f 2>/dev/null)
mkdir -p $(dir $@)
- $(VERILATOR) \
- -O3 --cc --exe -y $(RTL_DIR) --Mdir $(dir $@) \
- --top $(word 1,$(subst /, ,$*)) $(patsubst tb/%,../tb/%,$^) \
- $(VFLAGS)
+ $(VERILATOR) $(VFLAGS) \
+ --Mdir $(dir $@) --top $(word 1,$(subst /, ,$*)) \
+ $(filter %.sv %.cpp,$(patsubst tb/%,../tb/%,$^)) \
+ $(if $(filter $(TOP),$(word 1,$(subst /, ,$*))),, \
+ --vpi --public-flat-rw -LDFLAGS "$(COCOTB_LDFLAGS) $(LIBPYTHON)" \
+ $(shell $(COCOTB_CONFIG) --share)/lib/verilator/verilator.cpp)
diff --git a/flake.nix b/flake.nix
index 2d6e5db..3ad2d91 100644
--- a/flake.nix
+++ b/flake.nix
@@ -136,7 +136,14 @@
kermit
lcov
pkg-config
- (python3.withPackages (py: [ py.numpy py.pillow py.matplotlib ]))
+ (python3.withPackages (py: with py; [
+ cocotb
+ find-libpython # Para cocotb
+ matplotlib
+ numpy
+ pillow
+ pytest # Para cocotb
+ ]))
(quartus-prime-lite.override { supportedDevices = [ "Cyclone V" ]; })
verilator
];
diff --git a/rtl/top/decode_test.sv b/rtl/top/decode_test.sv
deleted file mode 100644
index 91962ea..0000000
--- a/rtl/top/decode_test.sv
+++ /dev/null
@@ -1,14 +0,0 @@
-`timescale 1 ns / 1 ps
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module decode_test
-(
- input word insn,
-
- output insn_decode dec
-);
-
- core_decode DUT (.*);
-
-endmodule
diff --git a/rtl/top/fetch_test.sv b/rtl/top/fetch_test.sv
deleted file mode 100644
index 4ab5fd1..0000000
--- a/rtl/top/fetch_test.sv
+++ /dev/null
@@ -1,25 +0,0 @@
-`timescale 1 ns / 1 ps
-`include "core/uarch.sv"
-
-module fetch_test
-(
- input logic clk,
- stall,
- branch,
- prefetch_flush,
- fetched,
- wr_pc,
- input ptr branch_target,
- input word wr_current,
- fetch_data,
-
- output logic fetch,
- output word insn,
- output ptr insn_pc,
- addr
-
-);
-
- core_fetch #(.PREFETCH_ORDER(3)) DUT (.flush(), .*);
-
-endmodule
diff --git a/rtl/top/hps_sdram_test.sv b/rtl/top/hps_sdram_test.sv
deleted file mode 100644
index 28d6175..0000000
--- a/rtl/top/hps_sdram_test.sv
+++ /dev/null
@@ -1,93 +0,0 @@
-module hps_sdram_test
-(
- input wire clk_clk,
- output wire [12:0] memory_mem_a,
- output wire [2:0] memory_mem_ba,
- output wire memory_mem_ck,
- output wire memory_mem_ck_n,
- output wire memory_mem_cke,
- output wire memory_mem_cs_n,
- output wire memory_mem_ras_n,
- output wire memory_mem_cas_n,
- output wire memory_mem_we_n,
- output wire memory_mem_reset_n,
- inout wire [7:0] memory_mem_dq,
- inout wire memory_mem_dqs,
- inout wire memory_mem_dqs_n,
- output wire memory_mem_odt,
- output wire memory_mem_dm,
- input wire memory_oct_rzqin,
- /*input wire reset_reset_n,*/
-
- input logic dir, clr, mov, add, io,
- output logic[7:0] out,
- output logic done
-);
-
- wire reset_reset_n;
- assign reset_reset_n = 1'b1;
-
- enum {
- IDLE,
- IO,
- RELEASE
- } state;
-
- logic[29:0] addr;
- logic[31:0] data_rd, data_wr;
- logic ready, write, start;
-
- logic [7:0] leds;
-
- platform plat
- (
- .master_0_core_addr(addr),
- .master_0_core_data_rd(data_rd),
- .master_0_core_data_wr(data_wr),
- .master_0_core_ready(ready),
- .master_0_core_write(write),
- .master_0_core_start(start),
- .*
- );
-
- initial begin
- addr = 0;
- start = 0;
- state = IDLE;
- done = 0;
- end
-
- assign data_wr[7:0] = out;
- assign write = dir;
-
- always_ff @(posedge clk_clk) unique case(state)
- IDLE: begin
- state <= RELEASE;
-
- if(~clr)
- out <= 0;
- else if(~mov)
- addr <= dir ? addr + 1 : addr - 1;
- else if(~add)
- out <= dir ? out + 1 : out - 1;
- else if(~io) begin
- start <= 1;
- state <= IO;
- end
- end
-
- IO: begin
- done <= 1;
- start <= 0;
- if(ready) begin
- if(~dir) out <= data_rd[7:0];
- state <= RELEASE;
- end
- end
-
- RELEASE: begin
- done <= ~io;
- if(clr & mov & add & io) state <= IDLE;
- end
- endcase
-endmodule
diff --git a/rtl/top/mul_test.sv b/rtl/top/mul_test.sv
deleted file mode 100644
index 1395772..0000000
--- a/rtl/top/mul_test.sv
+++ /dev/null
@@ -1,33 +0,0 @@
-`timescale 1 ns / 1 ps
-
-module mul_test
-#(parameter U=32)
-(
- input logic[U - 1:0] a, // primer sumando
- b, // segundo sumando
- input logic[U - 1:0] c_hi, // parte más significativa de c
- c_lo, // parte menos significativa de c
- input logic c_size, // 1 si c es de 2 words, cualquier otro valor si c es de 1 word
- clk, // clock, ya que es una máquina de estados
- rst, // reset
- add, // 1 si c se suma
- sig, // 1 si a y b son signed
- q_size, // 1 si q es de 2 words, cualquier otro valor si es de 1 word
- start, // 1 indica que se inicie la multiplicacion
-
- output logic [U - 1:0] q_hi, // parte más significativa del resultado
- output logic [U - 1:0] q_lo, // parte menos significativa del resultado
- output logic [2*U-1:0] result,
- output logic n, // no hay C ni V, ya que se dejan unaffected
- z,
- q_sig, // 1 si q es signed, cualquier otro valor si es unsigned
- rdy // 1 cuando la multiplicación está lista
-
-
-);
- core_mul #(.U(U)) DUT (.*);
-
-endmodule
-
-
-
diff --git a/rtl/top/smp_sim.sv b/rtl/top/smp_sim.sv
new file mode 100644
index 0000000..137021c
--- /dev/null
+++ b/rtl/top/smp_sim.sv
@@ -0,0 +1,35 @@
+module smp_sim
+(
+ input logic clk,
+ rst_n,
+
+ input logic avl_read,
+ avl_write,
+ input logic[31:0] avl_writedata,
+ output logic[31:0] avl_readdata,
+
+ input logic cpu_halted_0,
+ cpu_halted_1,
+ cpu_halted_2,
+ cpu_halted_3,
+ input logic breakpoint_0,
+ breakpoint_1,
+ breakpoint_2,
+ breakpoint_3,
+
+ output logic halt_0,
+ halt_1,
+ halt_2,
+ halt_3,
+ step_0,
+ step_1,
+ step_2,
+ step_3
+);
+
+ smp_ctrl dut
+ (
+ .*
+ );
+
+endmodule
diff --git a/tb/__init__.py b/tb/__init__.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tb/__init__.py
diff --git a/tb/top/__init__.py b/tb/top/__init__.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tb/top/__init__.py
diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp
index a0de8f4..198cc30 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion.cpp
@@ -16,41 +16,41 @@
#include <verilated_fst_c.h>
#endif
-#include "Vconspiracion.h"
-#include "Vconspiracion_arm810.h"
-#include "Vconspiracion_conspiracion.h"
-#include "Vconspiracion_platform.h"
-#include "Vconspiracion_sim_slave.h"
-#include "Vconspiracion_vga_domain.h"
-#include "Vconspiracion_core.h"
-#include "Vconspiracion_core_control.h"
-#include "Vconspiracion_core_control_issue.h"
-#include "Vconspiracion_core_cp15_domain.h"
-#include "Vconspiracion_core_cp15_far.h"
-#include "Vconspiracion_core_cp15_fsr.h"
-#include "Vconspiracion_core_cp15_syscfg.h"
-#include "Vconspiracion_core_cp15_ttbr.h"
-#include "Vconspiracion_core_cp15.h"
-#include "Vconspiracion_core_fetch.h"
-#include "Vconspiracion_core_mmu.h"
-#include "Vconspiracion_core_psr.h"
-#include "Vconspiracion_core_regs.h"
-#include "Vconspiracion_core_reg_file.h"
-#include "Vconspiracion_cache.h"
-#include "Vconspiracion_cache__T1.h"
-#include "Vconspiracion_cache_sram.h"
-
-#include "../args.hxx"
-
-#include "../avalon.hpp"
-#include "../const.hpp"
-#include "../mem.hpp"
-#include "../jtag_uart.hpp"
-#include "../interval_timer.hpp"
-#include "../null.hpp"
-#include "../sim_slave.hpp"
-#include "../window.hpp"
-#include "../vga.hpp"
+#include "Vtop.h"
+#include "Vtop_arm810.h"
+#include "Vtop_conspiracion.h"
+#include "Vtop_platform.h"
+#include "Vtop_sim_slave.h"
+#include "Vtop_vga_domain.h"
+#include "Vtop_core.h"
+#include "Vtop_core_control.h"
+#include "Vtop_core_control_issue.h"
+#include "Vtop_core_cp15_domain.h"
+#include "Vtop_core_cp15_far.h"
+#include "Vtop_core_cp15_fsr.h"
+#include "Vtop_core_cp15_syscfg.h"
+#include "Vtop_core_cp15_ttbr.h"
+#include "Vtop_core_cp15.h"
+#include "Vtop_core_fetch.h"
+#include "Vtop_core_mmu.h"
+#include "Vtop_core_psr.h"
+#include "Vtop_core_regs.h"
+#include "Vtop_core_reg_file.h"
+#include "Vtop_cache.h"
+#include "Vtop_cache__T1.h"
+#include "Vtop_cache_sram.h"
+
+#include "args.hxx"
+
+#include "avalon.hpp"
+#include "const.hpp"
+#include "mem.hpp"
+#include "jtag_uart.hpp"
+#include "interval_timer.hpp"
+#include "null.hpp"
+#include "sim_slave.hpp"
+#include "window.hpp"
+#include "vga.hpp"
namespace
{
@@ -307,7 +307,7 @@ int main(int argc, char **argv)
dup2(*control_fd, STDERR_FILENO);
}
- Vconspiracion top;
+ Vtop top;
#if VM_TRACE
VerilatedFstC trace;
@@ -335,8 +335,8 @@ int main(int argc, char **argv)
null vram_null(0x3800'0000, 64 << 20, 2);
window vram_window(vram, 0x0000'0000);
- Vconspiracion_platform &plat = *top.conspiracion->plat;
- display<Vconspiracion_vga_domain> vga
+ Vtop_platform &plat = *top.conspiracion->plat;
+ display<Vtop_vga_domain> vga
(
*plat.vga, 0x3800'0000, 25'175'000, 50'000'000
);
@@ -347,8 +347,8 @@ int main(int argc, char **argv)
sim_slave dbg_3(*plat.smp_dbg_3, 0x3013'0000, 32);
sim_slave smp_ctrl(*plat.smp_sim, 0x3014'0000, 4);
- interconnect<Vconspiracion_platform> avl(plat);
- //interconnect<Vconspiracion_vga_domain> avl_vga(plat->vga);
+ interconnect<Vtop_platform> avl(plat);
+ //interconnect<Vtop_vga_domain> avl_vga(plat->vga);
std::vector<const_map> consts;
for(const auto &init : *const_)
@@ -411,14 +411,14 @@ int main(int argc, char **argv)
std::fclose(img_file);
}
- Vconspiracion_arm810 *const cores[] = {
+ Vtop_arm810 *const cores[] = {
plat.cpu_0->cpu,
plat.cpu_1->cpu,
plat.cpu_2->cpu,
plat.cpu_3->cpu
};
- Vconspiracion_cache_sram *const caches[] = {
+ Vtop_cache_sram *const caches[] = {
plat.cache_0->sram,
plat.cache_1->sram,
plat.cache_2->sram,
diff --git a/tb/args.hxx b/tb/top/conspiracion/args.hxx
index 69ccbf6..69ccbf6 100644
--- a/tb/args.hxx
+++ b/tb/top/conspiracion/args.hxx
diff --git a/tb/platform.sv b/tb/top/conspiracion/platform.sv
index bbf1088..bbf1088 100644
--- a/tb/platform.sv
+++ b/tb/top/conspiracion/platform.sv
diff --git a/tb/sim_slave.cpp b/tb/top/conspiracion/sim_slave.cpp
index 24528d2..24528d2 100644
--- a/tb/sim_slave.cpp
+++ b/tb/top/conspiracion/sim_slave.cpp
diff --git a/tb/sim_slave.hpp b/tb/top/conspiracion/sim_slave.hpp
index cdcea78..12cec62 100644
--- a/tb/sim_slave.hpp
+++ b/tb/top/conspiracion/sim_slave.hpp
@@ -3,13 +3,13 @@
#include <cstdint>
-#include "Vconspiracion_sim_slave.h"
+#include "Vtop_sim_slave.h"
#include "avalon.hpp"
namespace taller::avalon
{
- using verilated_slave = Vconspiracion_sim_slave;
+ using verilated_slave = Vtop_sim_slave;
class sim_slave : public slave
{
diff --git a/tb/sim_slave.sv b/tb/top/conspiracion/sim_slave.sv
index 1598701..1598701 100644
--- a/tb/sim_slave.sv
+++ b/tb/top/conspiracion/sim_slave.sv
diff --git a/tb/vga_domain.sv b/tb/top/conspiracion/vga_domain.sv
index 0c9aac5..0c9aac5 100644
--- a/tb/vga_domain.sv
+++ b/tb/top/conspiracion/vga_domain.sv
diff --git a/tb/top/decode_test.cpp b/tb/top/decode_test.cpp
deleted file mode 100644
index 4b78535..0000000
--- a/tb/top/decode_test.cpp
+++ /dev/null
@@ -1,101 +0,0 @@
-#include <cstdio>
-
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-
-#include "Vdecode_test.h" // From Verilating "top.v"
-
-int main(int argc, char** argv) {
- Verilated::commandArgs(argc, argv); // Remember args
- Verilated::traceEverOn(true);
-
- Vdecode_test top;
- VerilatedVcdC trace;
-
- top.trace(&trace, 0);
- trace.open("decode_test.vcd");
-
- // sim/control_flow.c
- uint32_t rom[] =
- {
- 0xea000032,
- 0xea000034,
- 0xea000000,
- 0xeafffffe,
- 0xeafffffe,
- 0xeafffffe,
- 0xeafffffe,
- 0xe3500000,
- 0xda000001,
- 0xe3a00001,
- 0xe1a0f00e,
- 0x13e00000,
- 0x03a00000,
- 0xe1a0f00e,
- 0xe1a02000,
- 0xe92d4010,
- 0xe1a00002,
- 0xebfffff4,
- 0xe1a03000,
- 0xe1a00001,
- 0xebfffff1,
- 0xe0933000,
- 0x0a00000c,
- 0xe3730001,
- 0x0a00000e,
- 0xe3530001,
- 0x0a00000a,
- 0xe1a038a1,
- 0xe1a00502,
- 0xe1833601,
- 0xe02023c2,
- 0xe0831001,
- 0xe1520001,
- 0xcaffffed,
- 0xe0820001,
- 0xe8bd8010,
- 0xe1a02822,
- 0xe1822801,
- 0xe1a00f62,
- 0xe8bd8010,
- 0xe3500000,
- 0xda000002,
- 0xe1a02001,
- 0xe2611001,
- 0xeafffff2,
- 0xe1e02001,
- 0xe1a00002,
- 0xebffffd6,
- 0xe3500000,
- 0xdaffffed,
- 0xe1a01002,
- 0xeafffff5,
- 0xe59fd008,
- 0xebffffd7,
- 0xeafffffe,
- 0xeafffffe,
- 0x20000000,
- };
-
- int clk_tick = 0;
- int time = 0;
-
- for(int i = 0; i < sizeof(rom)/sizeof(rom[0]); ++i)
- {
- top.insn = rom[i];
-
- top.eval();
- trace.dump(time++);
-
- std::printf("insn=0x%08x, dec=0x", top.insn);
- for(std::size_t j = 0; j < sizeof(top.dec) / sizeof(top.dec[0]); ++j)
- {
- std::printf("%08x", top.dec[j]);
- }
-
- std::puts("");
- }
-
- trace.close();
- top.final(); // Done simulating
-}
diff --git a/tb/top/fetch_test.cpp b/tb/top/fetch_test.cpp
deleted file mode 100644
index 06768c4..0000000
--- a/tb/top/fetch_test.cpp
+++ /dev/null
@@ -1,166 +0,0 @@
-#include <cstdio>
-
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-
-#include "Vfetch_test.h" // From Verilating "top.v"
-
-int main(int argc, char** argv) {
- Verilated::commandArgs(argc, argv); // Remember args
- Verilated::traceEverOn(true);
-
- Vfetch_test top;
- VerilatedVcdC trace;
-
- top.trace(&trace, 0);
- trace.open("fetch_test.vcd");
-
- top.clk = 0;
- top.stall = 0; //insn y insn_pc se detienen
- top.branch = 0; //forma de flush -> instr saltan a la instr de la branch
- top.prefetch_flush = 0; //limpia prefetch
- top.fetched = 1; //estado del fetch (ready)
- top.wr_pc = 0; //cuando hay un write al pc
- top.branch_target = 0; //direccion a la que se hace salto
- top.wr_current = 0; //ultimo que se guardo en registros
- top.fetch_data = 0x00000000; //data que se leyó al hacer fetch
-
- uint32_t rom[] =
- {
- 0xea000032,
- 0xea000034,
- 0xea000000,
- 0xeafffffe,
- 0xeafffffe,
- 0xeafffffe,
- 0xeafffffe,
- 0xe3500000,
- 0xda000001,
- 0xe3a00001,
- 0xe1a0f00e,
- 0x13e00000,
- 0x03a00000,
- 0xe1a0f00e,
- 0xe1a02000,
- 0xe92d4010,
- 0xe1a00002,
- 0xebfffff4,
- 0xe1a03000,
- 0xe1a00001,
- 0xebfffff1,
- 0xe0933000,
- 0x0a00000c,
- 0xe3730001,
- 0x0a00000e,
- 0xe3530001,
- 0x0a00000a,
- 0xe1a038a1,
- 0xe1a00502,
- 0xe1833601,
- 0xe02023c2,
- 0xe0831001,
- 0xe1520001,
- 0xcaffffed,
- 0xe0820001,
- 0xe8bd8010,
- 0xe1a02822,
- 0xe1822801,
- 0xe1a00f62,
- 0xe8bd8010,
- 0xe3500000,
- 0xda000002,
- 0xe1a02001,
- 0xe2611001,
- 0xeafffff2,
- 0xe1e02001,
- 0xe1a00002,
- 0xebffffd6,
- 0xe3500000,
- 0xdaffffed,
- 0xe1a01002,
- 0xeafffff5,
- 0xe59fd008,
- 0xebffffd7,
- 0xeafffffe,
- 0xeafffffe,
- 0x20000000,
- };
-
- int clk_tick = 0;
- int time = 0;
-
- std::printf("CPU cycle:\n");
- while (time < 50)
- {
- top.eval();
- trace.dump(time++);
-
- if(!top.clk)
- {
- std::printf("insn=0x%08x, insn_pc=0x%08x, addr=0x%08x\n",
- top.insn, top.insn_pc, top.addr);
- }
-
- top.clk = !top.clk;
-
- top.fetch_data = rom[top.addr];
- }
-
- std::printf("Branch, flush, stall:\n");
- while (time < 99)
- {
- top.eval();
- trace.dump(time++);
-
- if(!top.clk)
- {
- std::printf("insn=0x%08x, insn_pc=0x%08x, addr=0x%08x\n",
- top.insn, top.insn_pc, top.addr);
- }
-
- top.clk = !top.clk;
-
- if(time == 55)
- {
- std::printf("Se hace un branch:\n");
- top.branch = 1;
- top.branch_target = 3;
- }
-
- if(time == 59)
- {
- std::printf("Se termina el branch:\n");
- top.branch = 0;
-
- }
-
- if(time == 63){
- std::printf("Se hace un flush:\n");
- top.branch = 0;
- top.branch_target = 0;
- top.prefetch_flush = 1;
- }
-
- if(time == 69){
- std::printf("Se termina el flush:\n");
- top.prefetch_flush = 0;
- }
-
- if(time == 75)
- {
- std::printf("Se hace un stall:\n");
- top.stall = 1;
- }
-
- if(time == 81)
- {
- std::printf("Se termina el stall:\n");
- top.stall = 0;
- }
-
- top.fetch_data = rom[top.addr];
- }
-
- trace.close();
- top.final(); // Done simulating
-}
diff --git a/tb/top/hps_sdram_test.cpp b/tb/top/hps_sdram_test.cpp
deleted file mode 100644
index b173c41..0000000
--- a/tb/top/hps_sdram_test.cpp
+++ /dev/null
@@ -1,93 +0,0 @@
-#include <cstdio>
-
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-
-#include "Vhps_sdram_test.h"
-#include "Vhps_sdram_test_hps_sdram_test.h"
-#include "Vhps_sdram_test_platform.h"
-
-#include "../avalon.hpp"
-#include "../mem.hpp"
-
-int main(int argc, char **argv)
-{
- using namespace taller::avalon;
-
- Verilated::commandArgs(argc, argv);
-
- Vhps_sdram_test top;
-
-#ifdef TRACE
- Verilated::traceEverOn(true);
- VerilatedVcdC trace;
-
- top.trace(&trace, 0);
- trace.open("trace.vcd");
-#endif
-
- interconnect<Vhps_sdram_test_platform> avl(*top.hps_sdram_test->plat);
- mem hps_ddr3(0x0000'0000, 512 << 20);
-
- avl.attach(hps_ddr3);
-
- int time = 0;
- top.clk_clk = 1;
-
- auto tick = [&]()
- {
- top.clk_clk = !top.clk_clk;
- top.eval();
- avl.tick(top.clk_clk);
-#ifdef TRACE
- trace.dump(time++);
-#endif
- };
-
- auto cycle = [&]()
- {
- tick();
- tick();
- std::printf("[%02d] out=0x%02x, done=%d\n", time, top.out, top.done);
- };
-
- auto io = [&]()
- {
- top.io = 0;
- cycle();
- top.io = 1;
- for(int i = 0; i < 4; ++i)
- {
- cycle();
- }
- };
-
- top.dir = 1;
- top.io = 1;
- top.mov = 1;
- top.clr = 1;
-
- for(int i = 0; i < 5; ++i)
- {
- top.add = 0;
- cycle();
- top.add = 1;
- cycle();
- }
-
- io();
-
- top.clr = 0;
- cycle();
- top.clr = 1;
- cycle();
-
- top.dir = 0;
- io();
-
-#ifdef TRACE
- trace.close();
-#endif
-
- top.final();
-}
diff --git a/tb/top/mul_test.cpp b/tb/top/mul_test.cpp
deleted file mode 100644
index cd99760..0000000
--- a/tb/top/mul_test.cpp
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <cstdio>
-
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-
-#include "Vmul_test.h" // From Verilating "top.v"
-
-int main(int argc, char** argv) {
- Verilated::commandArgs(argc, argv); // Remember args
- Verilated::traceEverOn(true);
-
- Vmul_test top;
- VerilatedVcdC trace;
-
- top.trace(&trace, 0);
- trace.open("mul_test.vcd");
-
- top.a = 6;
- top.b = 5;
- top.clk = 0;
- top.rst = 0;
- top.start = 0;
- top.result = 0;
- top.rdy = 0;
- top.c_hi = 0;
- top.c_lo = 0;
-
-
- int clk_tick = 0;
- int time = 0;
-
- for(int i = 0; i < 100; ++i)
- {
- if(++clk_tick == 5)
- {
- clk_tick = 0;
- top.clk = !top.clk;
- }
-
-
- if(++clk_tick == 10)
- {
- top.rst = 1;
- }
-
- if(++clk_tick == 20)
- {
- top.start = 1;
- }
-
- if(++clk_tick == 30)
- {
- top.start = 0;
- }
-
- top.eval();
- trace.dump(time++);
-
- std::printf(" [%c%c%c%c]\n",
- top.n ? 'N' : 'n',
- top.z ? 'Z' : 'z',
- top.c ? 'C' : 'c',
- top.v ? 'V' : 'v');
-
- std::printf("a=%d, b=%d, ready=%d, result=%d, [N=%d, Z=%d]",
- top.a, top.b, top.rdy, top.result, top.n, top.z);
- }
-
- trace.close();
- top.final(); // Done simulating
-} \ No newline at end of file
diff --git a/tb/top/smp_sim.cpp b/tb/top/smp_sim.cpp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tb/top/smp_sim.cpp
diff --git a/tb/top/smp_sim.py b/tb/top/smp_sim.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tb/top/smp_sim.py
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 06:53:42 +0000