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authorAlejandro Soto <alejandro@34project.org>2024-05-04 14:19:48 -0600
committerAlejandro Soto <alejandro@34project.org>2024-05-04 14:19:48 -0600
commita7d92072c0bdc3a3e1c99de64f353e932846bc2a (patch)
treecc9af86b65820c3a30cf1d0b0c97e8bfe8fc9b44 /rtl/pkt_switch/axi_bus.sv
parent90cd29d85865bb5a4dbdf791616818b151881883 (diff)
rtl/pkt_switch: replace axi_timer example with pkt_switch
Diffstat (limited to 'rtl/pkt_switch/axi_bus.sv')
-rw-r--r--rtl/pkt_switch/axi_bus.sv28
1 files changed, 28 insertions, 0 deletions
diff --git a/rtl/pkt_switch/axi_bus.sv b/rtl/pkt_switch/axi_bus.sv
new file mode 100644
index 0000000..f1460ca
--- /dev/null
+++ b/rtl/pkt_switch/axi_bus.sv
@@ -0,0 +1,28 @@
+//AXI interface bus
+interface axi_bus #(
+ parameter int unsigned AXI_ADDR_WIDTH = 32,
+ parameter int unsigned AXI_DATA_WIDTH = 32
+ );
+
+ logic [AXI_ADDR_WIDTH-1:0] ADDR;
+ logic AVALID;
+ logic AREADY;
+ logic AWRITE;
+ logic WVALID;
+ logic WREADY;
+ logic [AXI_DATA_WIDTH-1:0] WDATA;
+ logic RVALID;
+ logic RREADY;
+ logic [AXI_DATA_WIDTH-1:0] RDATA;
+
+ modport Master(
+ input AREADY, WREADY, RVALID, RDATA,
+ output ADDR, AVALID, AWRITE, WVALID, WDATA, RREADY
+ );
+
+ modport Slave(
+ input ADDR, AVALID, AWRITE, WVALID, WDATA, RREADY,
+ output AREADY, WREADY, RVALID, RDATA
+ );
+
+endinterface