diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-10-29 18:59:33 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-29 19:48:23 -0600 |
| commit | eed877444f9af85d6e4596853d8f188e61f6c4ed (patch) | |
| tree | 53f54a96b006f4a3d0fa952292408e7d63f81a61 /rtl/gfx/gfx.sv | |
| parent | adabbf5f30729092a64fa1059bbc7d7b09d6b24e (diff) | |
rtl/gfx: implement scanout command interface
Diffstat (limited to 'rtl/gfx/gfx.sv')
| -rw-r--r-- | rtl/gfx/gfx.sv | 94 |
1 files changed, 4 insertions, 90 deletions
diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv index 7749c50..fcaaffb 100644 --- a/rtl/gfx/gfx.sv +++ b/rtl/gfx/gfx.sv @@ -26,43 +26,11 @@ module gfx output rgb30 scan_data ); - fp readdata, writedata; - mat4 a, b, q, hold_q; - logic start, done; - - assign mem_read = 1; - assign mem_write = 0; - - assign readdata = hold_q[cmd_address[3:2]][cmd_address[1:0]]; - assign writedata = cmd_writedata[`FLOAT_BITS - 1:0]; - - always_comb begin - if (!cmd_address[5]) - cmd_readdata = {{($bits(cmd_readdata) - `FLOAT_BITS){1'b0}}, readdata}; - else if (cmd_address[4]) - cmd_readdata = cmd_address[0] ? cnt_done : cnt_start; - else - unique case (cmd_address[1:0]) - 2'b00: - cmd_readdata = snp_trans[31:0]; - - 2'b01: - cmd_readdata = snp_trans[63:32]; - - 2'b10: - cmd_readdata = snp_cycles[31:0]; - - 2'b11: - cmd_readdata = snp_cycles[63:32]; - endcase - end + logic enable_clear, swap_buffers; + rgb24 clear_color; - mat_mat_mul mul + gfx_cmd cmd ( - .in_ready(), - .in_valid(start), - .out_ready(1), - .out_valid(done), .* ); @@ -77,18 +45,9 @@ module gfx .* ); - logic swap_buffers; - rgb24 clear_color; - - assign swap_buffers = 0; - assign clear_color.r = 255; - assign clear_color.g = 0; - assign clear_color.b = 0; - + logic scanout_read_tmp, vsync; linear_coord scan_mask_addr; - logic scanout_read_tmp; - gfx_scanout scanout ( .mask(scan_mask), @@ -103,49 +62,4 @@ module gfx .* ); - logic[63:0] cnt_cycles, cnt_trans, snp_cycles, snp_trans; - logic[24:0] cnt_addr; - logic[31:0] cnt_done, cnt_start; - assign mem_address = {cnt_addr, 1'b0}; - - always_ff @(posedge clk) begin - if (cmd_write) begin - if (cmd_address[4]) - b[cmd_address[3:2]][cmd_address[1:0]] <= writedata; - else - a[cmd_address[3:2]][cmd_address[1:0]] <= writedata; - - snp_trans <= cnt_trans; - snp_cycles <= cnt_cycles; - end - - if (done) - hold_q <= q; - end - - always_ff @(posedge clk or negedge rst_n) - if (!rst_n) begin - start <= 0; - cnt_addr <= 0; - cnt_trans <= 0; - cnt_cycles <= 0; - cnt_done <= 0; - cnt_start <= 0; - end else begin - start <= cmd_write; - cnt_cycles <= cnt_cycles + 1; - - if (start) - cnt_start <= cnt_start + 1; - - if (done) - cnt_done <= cnt_done + 1; - - if (!mem_waitrequest) - cnt_addr <= cnt_addr + 1; - - if (mem_readdatavalid) - cnt_trans <= cnt_trans + 1; - end - endmodule |
