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authorAlejandro Soto <alejandro@34project.org>2024-02-28 16:44:15 -0600
committerAlejandro Soto <alejandro@34project.org>2024-03-03 20:42:36 -0600
commitcce507d21c86f20a83eec1b09fe3231399ffb10c (patch)
treecef497f3eb1767aeb9d8817adbbed467eac3b72d /rtl/dma_axi32/prgen_min3.v
parent872349eb3a3a508abee028e75da546692eb8e0e7 (diff)
rtl/dma_axi32: fix verilator warnings
Diffstat (limited to 'rtl/dma_axi32/prgen_min3.v')
-rw-r--r--rtl/dma_axi32/prgen_min3.v12
1 files changed, 8 insertions, 4 deletions
diff --git a/rtl/dma_axi32/prgen_min3.v b/rtl/dma_axi32/prgen_min3.v
index 2726655..bfcf6d1 100644
--- a/rtl/dma_axi32/prgen_min3.v
+++ b/rtl/dma_axi32/prgen_min3.v
@@ -1,3 +1,5 @@
+// verilator lint_off WIDTHEXPAND
+// verilator lint_off WIDTHTRUNC
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
@@ -68,13 +70,13 @@ module prgen_min3(clk,reset,a,b,c,min);
always @(posedge clk or posedge reset)
if (reset)
begin
- min_ab <= #1 {WIDTH{1'b0}};
- min_c <= #1 {WIDTH{1'b0}};
+ min_ab <= {WIDTH{1'b0}};
+ min_c <= {WIDTH{1'b0}};
end
else
begin
- min_ab <= #1 min_ab_pre;
- min_c <= #1 c;
+ min_ab <= min_ab_pre;
+ min_c <= c;
end
endmodule
@@ -83,3 +85,5 @@ endmodule
+// verilator lint_on WIDTHEXPAND
+// verilator lint_on WIDTHTRUNC