blob: 2726655be205a0cbc2846a31127f83a4e7241e07 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:34:53 2011
//--
//-- Source file: prgen_min3.v
//---------------------------------------------------------
module prgen_min3(clk,reset,a,b,c,min);
parameter WIDTH = 8;
input clk;
input reset;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input [WIDTH-1:0] c;
output [WIDTH-1:0] min;
wire [WIDTH-1:0] min_ab_pre;
reg [WIDTH-1:0] min_ab;
reg [WIDTH-1:0] min_c;
prgen_min2 #(WIDTH) min2_ab(
.a(a),
.b(b),
.min(min_ab_pre)
);
prgen_min2 #(WIDTH) min2_abc(
.a(min_ab),
.b(min_c),
.min(min)
);
always @(posedge clk or posedge reset)
if (reset)
begin
min_ab <= #1 {WIDTH{1'b0}};
min_c <= #1 {WIDTH{1'b0}};
end
else
begin
min_ab <= #1 min_ab_pre;
min_c <= #1 c;
end
endmodule
|
