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authorAlejandro Soto <alejandro@34project.org>2024-02-28 16:44:15 -0600
committerAlejandro Soto <alejandro@34project.org>2024-03-03 20:42:36 -0600
commitcce507d21c86f20a83eec1b09fe3231399ffb10c (patch)
treecef497f3eb1767aeb9d8817adbbed467eac3b72d /rtl/dma_axi32/prgen_delay.v
parent872349eb3a3a508abee028e75da546692eb8e0e7 (diff)
rtl/dma_axi32: fix verilator warnings
Diffstat (limited to 'rtl/dma_axi32/prgen_delay.v')
-rw-r--r--rtl/dma_axi32/prgen_delay.v8
1 files changed, 6 insertions, 2 deletions
diff --git a/rtl/dma_axi32/prgen_delay.v b/rtl/dma_axi32/prgen_delay.v
index 5855f4e..785746a 100644
--- a/rtl/dma_axi32/prgen_delay.v
+++ b/rtl/dma_axi32/prgen_delay.v
@@ -1,3 +1,5 @@
+// verilator lint_off WIDTHEXPAND
+// verilator lint_off WIDTHTRUNC
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
@@ -52,9 +54,9 @@ module prgen_delay(clk,reset,din,dout);
always @(posedge clk or posedge reset)
if (reset)
- shift_reg <= #1 {DELAY+1{1'b0}};
+ shift_reg <= {DELAY+1{1'b0}};
else
- shift_reg <= #1 {shift_reg[DELAY-1:0], din};
+ shift_reg <= {shift_reg[DELAY-1:0], din};
assign dout = shift_reg[DELAY-1];
@@ -68,3 +70,5 @@ endmodule
+// verilator lint_on WIDTHEXPAND
+// verilator lint_on WIDTHTRUNC