summaryrefslogtreecommitdiff
path: root/rtl/dma_axi32/prgen_delay.v
diff options
context:
space:
mode:
authorAlejandro Soto <alejandro@34project.org>2024-02-28 16:07:44 -0600
committerAlejandro Soto <alejandro@34project.org>2024-03-03 20:42:36 -0600
commit872349eb3a3a508abee028e75da546692eb8e0e7 (patch)
treeacdab5296943bb067bae849f82e3d4756ed14635 /rtl/dma_axi32/prgen_delay.v
parent6e67445a93e97f6353aea0e8e79acf2b60b46985 (diff)
rtl: add dma_axi32
Diffstat (limited to 'rtl/dma_axi32/prgen_delay.v')
-rw-r--r--rtl/dma_axi32/prgen_delay.v70
1 files changed, 70 insertions, 0 deletions
diff --git a/rtl/dma_axi32/prgen_delay.v b/rtl/dma_axi32/prgen_delay.v
new file mode 100644
index 0000000..5855f4e
--- /dev/null
+++ b/rtl/dma_axi32/prgen_delay.v
@@ -0,0 +1,70 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Author: Eyal Hochberg ////
+//// eyal@provartec.com ////
+//// ////
+//// Downloaded from: http://www.opencores.org ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2010 Provartec LTD ////
+//// www.provartec.com ////
+//// info@provartec.com ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation.////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more////
+//// details. http://www.gnu.org/licenses/lgpl.html ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//---------------------------------------------------------
+//-- File generated by RobustVerilog parser
+//-- Version: 1.0
+//-- Invoked Fri Mar 25 23:34:54 2011
+//--
+//-- Source file: prgen_delay.v
+//---------------------------------------------------------
+
+
+
+module prgen_delay(clk,reset,din,dout);
+
+
+ input clk;
+ input reset;
+
+ input din;
+ output dout;
+
+ parameter DELAY = 2;
+
+
+ reg [DELAY:0] shift_reg;
+
+ always @(posedge clk or posedge reset)
+ if (reset)
+ shift_reg <= #1 {DELAY+1{1'b0}};
+ else
+ shift_reg <= #1 {shift_reg[DELAY-1:0], din};
+
+ assign dout = shift_reg[DELAY-1];
+
+
+endmodule
+
+
+
+
+
+
+
+