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| author | Alejandro Soto <alejandro@34project.org> | 2022-10-09 14:34:48 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-09 14:34:48 -0600 |
| commit | 1f1f61bbab1396278a861e46fd65a50d1914585e (patch) | |
| tree | b8ba06e3f891cc42b6bf73abbd58fd33e7898b7b /rtl/core/regs | |
| parent | 4ea1cd32da476616c66799d210913b001772a1e2 (diff) | |
Pipeline flags writeback (breaks combinational data dependencies)
Diffstat (limited to 'rtl/core/regs')
| -rw-r--r-- | rtl/core/regs/regs.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv index 6ddf335..9b9ba57 100644 --- a/rtl/core/regs/regs.sv +++ b/rtl/core/regs/regs.sv @@ -29,7 +29,7 @@ module core_regs assign pc_word = {pc_visible, 2'b00}; assign rd_value_a = rd_pc_a ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_a; - assign rd_value_b = rd_pc_b ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_b; + assign rd_value_b = rd_pc_b ? pc_word : (wr_enable && rd_index_b == wr_index) ? wr_value : file_rd_value_b; assign file_wr_enable = wr_enable & ~wr_pc; assign branch = wr_enable & wr_pc; |