From 1f1f61bbab1396278a861e46fd65a50d1914585e Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 9 Oct 2022 14:34:48 -0600 Subject: Pipeline flags writeback (breaks combinational data dependencies) --- rtl/core/regs/regs.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'rtl/core/regs') diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv index 6ddf335..9b9ba57 100644 --- a/rtl/core/regs/regs.sv +++ b/rtl/core/regs/regs.sv @@ -29,7 +29,7 @@ module core_regs assign pc_word = {pc_visible, 2'b00}; assign rd_value_a = rd_pc_a ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_a; - assign rd_value_b = rd_pc_b ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_b; + assign rd_value_b = rd_pc_b ? pc_word : (wr_enable && rd_index_b == wr_index) ? wr_value : file_rd_value_b; assign file_wr_enable = wr_enable & ~wr_pc; assign branch = wr_enable & wr_pc; -- cgit v1.2.3