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authorAlejandro Soto <alejandro@34project.org>2022-11-10 10:11:33 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-10 10:11:33 -0600
commitacca3eb31a051f335c51306786bb972c21634998 (patch)
tree9f8fc3da1a8494e88c5043735862e56c54356bc0 /rtl/core/mmu
parent0f89db514bd174def590645c30a7bd358ea6be93 (diff)
Fix reset glitches
Diffstat (limited to 'rtl/core/mmu')
-rw-r--r--rtl/core/mmu/mmu.sv4
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv
index 185fb6b..cfb223f 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/mmu/mmu.sv
@@ -97,15 +97,15 @@ module core_mmu
if(hold_free)
unique case(next_master)
INSN: begin
- hold_start <= data_start;
hold_addr <= data_addr;
+ hold_start <= data_start;
hold_write <= data_write;
hold_data_wr <= data_data_wr;
end
DATA: begin
- hold_start <= insn_start;
hold_addr <= insn_addr;
+ hold_start <= insn_start;
hold_write <= 0;
end
endcase