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| author | Alejandro Soto <alejandro@34project.org> | 2022-12-12 11:47:02 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-16 16:29:10 -0600 |
| commit | c67d424c6d130f810c251576fd55389d1385edb5 (patch) | |
| tree | b274f3f80d0d06457696a53b35bb98bbfe572035 /rtl/core/cp15/syscfg.sv | |
| parent | 79e05aa7f0ccce6eb26248ddef3e928727857a9c (diff) | |
Show main cp15 registers in register dumps
Diffstat (limited to 'rtl/core/cp15/syscfg.sv')
| -rw-r--r-- | rtl/core/cp15/syscfg.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rtl/core/cp15/syscfg.sv b/rtl/core/cp15/syscfg.sv index d75f7ac..f7fc1a5 100644 --- a/rtl/core/cp15/syscfg.sv +++ b/rtl/core/cp15/syscfg.sv @@ -11,7 +11,7 @@ module core_cp15_syscfg input cp_opcode op2, input word write, - output word read, + output word read /*verilator public*/, output logic high_vectors, mmu_enable ); |