Implement rest of cp15 registers

1 files changed, 20 insertions, 0 deletions

diff --git a/rtl/core/cp15/fsr.sv b/rtl/core/cp15/fsr.sv
new file mode 100644
index 0000000..0a7d0d4
--- /dev/null
+++ b/rtl/core/cp15/fsr.sv
@@ -0,0 +1,20 @@
+`include "core/uarch.sv"
+`include "core/cp15/map.sv"
+
+module core_cp15_fsr
+(
+	input  logic     clk,
+	                 rst_n,
+
+	input  logic     load,
+	                 transfer,
+	input  cp_opcode op2,
+	input  word      write,
+
+	output word      read
+);
+
+	//TODO
+	assign read = 0;
+
+endmodule