From 8026947ecdf9b023c3720b26bf257bf46f7a2805 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 10 Dec 2022 19:36:38 -0600 Subject: Implement rest of cp15 registers --- rtl/core/cp15/fsr.sv | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 rtl/core/cp15/fsr.sv (limited to 'rtl/core/cp15/fsr.sv') diff --git a/rtl/core/cp15/fsr.sv b/rtl/core/cp15/fsr.sv new file mode 100644 index 0000000..0a7d0d4 --- /dev/null +++ b/rtl/core/cp15/fsr.sv @@ -0,0 +1,20 @@ +`include "core/uarch.sv" +`include "core/cp15/map.sv" + +module core_cp15_fsr +( + input logic clk, + rst_n, + + input logic load, + transfer, + input cp_opcode op2, + input word write, + + output word read +); + + //TODO + assign read = 0; + +endmodule -- cgit v1.2.3