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authorAlejandro Soto <alejandro@34project.org>2024-01-21 06:23:46 -0600
committerAlejandro Soto <alejandro@34project.org>2024-02-20 11:11:17 -0600
commitf3b18ead59ae02f95dabbf0a1dea40873a816975 (patch)
tree8979e50f2a37f66a4cd27e937b480efe60d72cf7 /rtl/core/cp15/far.sv
parenta8bc5a353ea997f73209b39377ee15a73e471237 (diff)
rtl: refactor filenames and directory hierarchy
Diffstat (limited to 'rtl/core/cp15/far.sv')
-rw-r--r--rtl/core/cp15/far.sv31
1 files changed, 0 insertions, 31 deletions
diff --git a/rtl/core/cp15/far.sv b/rtl/core/cp15/far.sv
deleted file mode 100644
index 36e76db..0000000
--- a/rtl/core/cp15/far.sv
+++ /dev/null
@@ -1,31 +0,0 @@
-`include "core/uarch.sv"
-`include "core/cp15/map.sv"
-
-module core_cp15_far
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write,
-
- input logic fault_register,
- input ptr fault_addr,
-
- output word read /*verilator public*/
-);
-
- word far;
-
- assign read = far;
-
- always @(posedge clk or negedge rst_n)
- if(!rst_n)
- far <= 0;
- else if(fault_register)
- far <= {fault_addr, 2'b00};
- else if(transfer && !load)
- far <= write;
-
-endmodule