diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-11 17:28:03 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-16 16:29:09 -0600 |
| commit | d006be2e89aa493237f212811ee880ed8b54241b (patch) | |
| tree | b8b9c25536c6f3b42920d3f9666610396e8f2404 /rtl/core/cp15/domain.sv | |
| parent | ff71bcd0c5425c168f111b8f4a92d0a90a6c9c31 (diff) | |
Implement MMU access checks
Diffstat (limited to 'rtl/core/cp15/domain.sv')
| -rw-r--r-- | rtl/core/cp15/domain.sv | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/rtl/core/cp15/domain.sv b/rtl/core/cp15/domain.sv index 4e5f5d6..92112be 100644 --- a/rtl/core/cp15/domain.sv +++ b/rtl/core/cp15/domain.sv @@ -9,16 +9,16 @@ module core_cp15_domain transfer, input word write, - output word read + output word read, + mmu_dac ); - word dac; - assign read = dac; + assign read = mmu_dac; always @(posedge clk or negedge rst_n) if(!rst_n) - dac <= 0; + mmu_dac <= 0; else if(transfer && !load) - dac <= write; + mmu_dac <= write; endmodule |