Implement rest of cp15 registers

1 files changed, 24 insertions, 0 deletions

diff --git a/rtl/core/cp15/domain.sv b/rtl/core/cp15/domain.sv
new file mode 100644
index 0000000..4e5f5d6
--- /dev/null
+++ b/rtl/core/cp15/domain.sv
@@ -0,0 +1,24 @@
+`include "core/uarch.sv"
+
+module core_cp15_domain
+(
+	input  logic     clk,
+	                 rst_n,
+
+	input  logic     load,
+	                 transfer,
+	input  word      write,
+
+	output word      read
+);
+
+	word dac;
+	assign read = dac;
+
+	always @(posedge clk or negedge rst_n)
+		if(!rst_n)
+			dac <= 0;
+		else if(transfer && !load)
+			dac <= write;
+
+endmodule