From 8026947ecdf9b023c3720b26bf257bf46f7a2805 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 10 Dec 2022 19:36:38 -0600 Subject: Implement rest of cp15 registers --- rtl/core/cp15/domain.sv | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 rtl/core/cp15/domain.sv (limited to 'rtl/core/cp15/domain.sv') diff --git a/rtl/core/cp15/domain.sv b/rtl/core/cp15/domain.sv new file mode 100644 index 0000000..4e5f5d6 --- /dev/null +++ b/rtl/core/cp15/domain.sv @@ -0,0 +1,24 @@ +`include "core/uarch.sv" + +module core_cp15_domain +( + input logic clk, + rst_n, + + input logic load, + transfer, + input word write, + + output word read +); + + word dac; + assign read = dac; + + always @(posedge clk or negedge rst_n) + if(!rst_n) + dac <= 0; + else if(transfer && !load) + dac <= write; + +endmodule -- cgit v1.2.3