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authorAlejandro Soto <alejandro@34project.org>2024-01-21 06:23:46 -0600
committerAlejandro Soto <alejandro@34project.org>2024-02-20 11:11:17 -0600
commitf3b18ead59ae02f95dabbf0a1dea40873a816975 (patch)
tree8979e50f2a37f66a4cd27e937b480efe60d72cf7 /rtl/core/core_reg_map.sv
parenta8bc5a353ea997f73209b39377ee15a73e471237 (diff)
rtl: refactor filenames and directory hierarchy
Diffstat (limited to 'rtl/core/core_reg_map.sv')
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1 files changed, 30 insertions, 0 deletions
diff --git a/rtl/core/core_reg_map.sv b/rtl/core/core_reg_map.sv
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+`include "core/uarch.sv"
+
+module core_reg_map
+(
+ input reg_num r,
+ input psr_mode mode,
+ output logic is_pc,
+ output reg_index index
+);
+
+ reg_index usr;
+ assign usr = {1'b0, r};
+
+ always_comb begin
+ index = 5'bxxxxx;
+ is_pc = r == `R15;
+
+ if(~is_pc)
+ unique case(mode)
+ `MODE_USR, `MODE_SYS: index = usr;
+ `MODE_FIQ: index = r >= 8 ? usr + 7 : usr;
+ `MODE_IRQ: index = r >= 13 ? usr + 9 : usr;
+ `MODE_UND: index = r >= 13 ? usr + 11 : usr;
+ `MODE_ABT: index = r >= 13 ? usr + 13 : usr;
+ `MODE_SVC: index = r >= 13 ? usr + 15 : usr;
+ default: ;
+ endcase
+ end
+
+endmodule