diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-01-21 06:23:46 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-02-20 11:11:17 -0600 |
| commit | f3b18ead59ae02f95dabbf0a1dea40873a816975 (patch) | |
| tree | 8979e50f2a37f66a4cd27e937b480efe60d72cf7 /rtl/core/core_cp15_cyclecnt.sv | |
| parent | a8bc5a353ea997f73209b39377ee15a73e471237 (diff) | |
rtl: refactor filenames and directory hierarchy
Diffstat (limited to 'rtl/core/core_cp15_cyclecnt.sv')
| -rw-r--r-- | rtl/core/core_cp15_cyclecnt.sv | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/rtl/core/core_cp15_cyclecnt.sv b/rtl/core/core_cp15_cyclecnt.sv new file mode 100644 index 0000000..b079a1b --- /dev/null +++ b/rtl/core/core_cp15_cyclecnt.sv @@ -0,0 +1,23 @@ +`include "core/uarch.sv" + +module core_cp15_cyclecnt +( + input logic clk, + rst_n, + + input logic halt, + + output word read +); + + word cyclecnt; + + assign read = cyclecnt; + + always @(posedge clk or negedge rst_n) + if(!rst_n) + cyclecnt <= 0; + else if(!halt) + cyclecnt <= cyclecnt + 1; + +endmodule |
