rtl: refactor filenames and directory hierarchy

1 files changed, 25 insertions, 0 deletions

diff --git a/rtl/core/core_control_debug.sv b/rtl/core/core_control_debug.sv
new file mode 100644
index 0000000..35b1334
--- /dev/null
+++ b/rtl/core/core_control_debug.sv
@@ -0,0 +1,25 @@
+`include "core/uarch.sv"
+
+module core_control_debug
+(
+	input  logic       clk,
+	                   rst_n,
+	                   step,
+
+	input  ctrl_cycle  next_cycle,
+	input  logic       issue,
+	                   next_bubble,
+	input  insn_decode dec,
+
+	output logic       breakpoint
+);
+
+	logic stable, step_trigger;
+
+	assign stable = next_cycle.issue && !dec.ctrl.nop && !next_bubble;
+	assign breakpoint = stable && (dec.ctrl.bkpt || step_trigger);
+
+	always @(posedge clk or negedge rst_n)
+		step_trigger <= !rst_n ? 0 : step && (step_trigger || stable) && !breakpoint;
+
+endmodule