Implement IRQ exceptions

2 files changed, 32 insertions, 15 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 840cf19..5f290d2 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -4,6 +4,8 @@ module core_control
 (
 	input  logic           clk,
 	                       rst_n,
+
+	input  logic           irq,
 	                       halt,
 	                       step,
 
@@ -11,6 +13,7 @@ module core_control
 	input  ptr             insn_pc,
 	input  logic           issue_abort,
 	input  psr_mode        mode,
+	input  psr_intmask     intmask,
 	input  psr_flags       flags,
 	                       alu_flags,
 	input  word            cpsr_rd,
diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv
index 038cd2b..76abc5c 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/control/exception.sv
@@ -5,11 +5,14 @@ module core_control_exception
 	input  logic      clk,
 	                  rst_n,
 
-	input  ctrl_cycle next_cycle,
-	input  logic      high_vectors,
-	                  undefined,
-	                  prefetch_abort,
-	                  mem_fault,
+	input  ctrl_cycle  next_cycle,
+	input  psr_intmask intmask,
+	input  logic       issue,
+	                   irq,
+	                   high_vectors,
+	                   undefined,
+	                   prefetch_abort,
+	                   mem_fault,
 
 	output logic      exception,
 	                  exception_offset_pc,
@@ -17,27 +20,38 @@ module core_control_exception
 	output word       exception_vector
 );
 
+	logic pending_irq;
 	logic[2:0] vector_offset;
 
 	//TODO: irq, fiq, prefetch abort, swi
 
-	assign exception = undefined || prefetch_abort || mem_fault;
+	assign exception = undefined || prefetch_abort || mem_fault || pending_irq;
 	assign exception_vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00};
 
 	always @(posedge clk or negedge rst_n) begin
 		if(!rst_n) begin
+			pending_irq <= 0;
 			vector_offset <= 0;
 			exception_mode <= 0;
 			exception_offset_pc <= 0;
-		end else if(mem_fault) begin
-			vector_offset <= 3'b100;
-			exception_mode <= `MODE_ABT;
-		end else if(prefetch_abort) begin
-			vector_offset <= 3'b011;
-			exception_mode <= `MODE_ABT;
-		end else if(undefined) begin
-			vector_offset <= 3'b001;
-			exception_mode <= `MODE_UND;
+		end begin
+			if(issue)
+				pending_irq <= irq && !intmask.i;
+
+			// A2.6.10 Exception priorities
+			if(mem_fault) begin
+				vector_offset <= 3'b100;
+				exception_mode <= `MODE_ABT;
+			end else if(pending_irq) begin
+				vector_offset <= 3'b110;
+				exception_mode <= `MODE_IRQ;
+			end else if(prefetch_abort) begin
+				vector_offset <= 3'b011;
+				exception_mode <= `MODE_ABT;
+			end else if(undefined) begin
+				vector_offset <= 3'b001;
+				exception_mode <= `MODE_UND;
+			end
 		end
 
 		if(next_cycle.escalate)