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authorAlejandro Soto <alejandro@34project.org>2024-01-21 06:23:46 -0600
committerAlejandro Soto <alejandro@34project.org>2024-02-20 11:11:17 -0600
commitf3b18ead59ae02f95dabbf0a1dea40873a816975 (patch)
tree8979e50f2a37f66a4cd27e937b480efe60d72cf7 /rtl/core/control/branch.sv
parenta8bc5a353ea997f73209b39377ee15a73e471237 (diff)
rtl: refactor filenames and directory hierarchy
Diffstat (limited to 'rtl/core/control/branch.sv')
-rw-r--r--rtl/core/control/branch.sv30
1 files changed, 0 insertions, 30 deletions
diff --git a/rtl/core/control/branch.sv b/rtl/core/control/branch.sv
deleted file mode 100644
index 0298b95..0000000
--- a/rtl/core/control/branch.sv
+++ /dev/null
@@ -1,30 +0,0 @@
-`include "core/uarch.sv"
-
-module core_control_branch
-(
- input logic clk,
- rst_n,
-
- input insn_decode dec,
-
- input ctrl_cycle next_cycle,
- input logic issue,
- input ptr next_pc_visible,
-
- output logic branch,
- output ptr branch_target
-);
-
- always_ff @(posedge clk or negedge rst_n)
- if(!rst_n) begin
- branch <= 1;
- branch_target <= {$bits(branch_target){1'b0}};
- end else begin
- branch <= 0;
- if(next_cycle.issue && issue) begin
- branch <= dec.ctrl.branch;
- branch_target <= next_pc_visible + dec.branch.offset;
- end
- end
-
-endmodule