diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-18 00:22:13 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-18 00:22:23 -0600 |
| commit | 6d458ad9629268ecfc69881b4fb10dca0498fbd0 (patch) | |
| tree | ea149276a31f518788c758899ab5ced8a8a8b74c /rtl/core/alu | |
| parent | ca8b6e6696e279f56faacad39501019c3762a1b7 (diff) | |
Fix datapath of shifter carry-out during adc/sbc/rsc
Diffstat (limited to 'rtl/core/alu')
| -rw-r--r-- | rtl/core/alu/alu.sv | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/rtl/core/alu/alu.sv b/rtl/core/alu/alu.sv index 2f71d6a..c0ccd32 100644 --- a/rtl/core/alu/alu.sv +++ b/rtl/core/alu/alu.sv @@ -8,6 +8,7 @@ module core_alu input logic[W - 1:0] a, b, input logic c_in, + c_logic, output logic[W - 1:0] q, output psr_flags nzcv, @@ -106,7 +107,7 @@ module core_alu v = 1'bx; unique case(op) `ALU_AND, `ALU_EOR, `ALU_TST, `ALU_TEQ, `ALU_ORR, `ALU_MOV, `ALU_BIC, `ALU_MVN: - c = c_in; + c = c_logic; `ALU_ADD, `ALU_ADC, `ALU_CMN: begin c = c_add; |