From 6d458ad9629268ecfc69881b4fb10dca0498fbd0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 18 Dec 2022 00:22:13 -0600
Subject: Fix datapath of shifter carry-out during adc/sbc/rsc

---
 rtl/core/alu/alu.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'rtl/core/alu')

diff --git a/rtl/core/alu/alu.sv b/rtl/core/alu/alu.sv
index 2f71d6a..c0ccd32 100644
--- a/rtl/core/alu/alu.sv
+++ b/rtl/core/alu/alu.sv
@@ -8,6 +8,7 @@ module core_alu
 	input  logic[W - 1:0] a,
 	                      b,
 	input  logic          c_in,
+	                      c_logic,
 
 	output logic[W - 1:0] q,
 	output psr_flags      nzcv,
@@ -106,7 +107,7 @@ module core_alu
 		v = 1'bx;
 		unique case(op)
 			`ALU_AND, `ALU_EOR, `ALU_TST, `ALU_TEQ, `ALU_ORR, `ALU_MOV, `ALU_BIC, `ALU_MVN:
-				c = c_in;
+				c = c_logic;
 
 			`ALU_ADD, `ALU_ADC, `ALU_CMN: begin
 				c = c_add;
-- 
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