rtl/axi_timer: initial commit

This a buggy timer, imported from https://github.com/astrakhov-design/axi_timer.
It will be used for a testbench hello world case

1 files changed, 28 insertions, 0 deletions

diff --git a/rtl/axi_timer/axi_bus.sv b/rtl/axi_timer/axi_bus.sv
new file mode 100644
index 0000000..f1460ca
--- /dev/null
+++ b/rtl/axi_timer/axi_bus.sv
@@ -0,0 +1,28 @@
+//AXI interface bus
+interface axi_bus #(
+  parameter int unsigned  AXI_ADDR_WIDTH  = 32,
+  parameter int unsigned  AXI_DATA_WIDTH  = 32
+  );
+
+  logic [AXI_ADDR_WIDTH-1:0] ADDR;
+  logic                      AVALID;
+  logic                      AREADY;
+  logic                      AWRITE;
+  logic                      WVALID;
+  logic                      WREADY;
+  logic [AXI_DATA_WIDTH-1:0] WDATA;
+  logic                      RVALID;
+  logic                      RREADY;
+  logic [AXI_DATA_WIDTH-1:0] RDATA;
+
+  modport Master(
+    input   AREADY, WREADY, RVALID, RDATA,
+    output  ADDR, AVALID, AWRITE, WVALID, WDATA, RREADY
+  );
+
+  modport Slave(
+    input   ADDR, AVALID, AWRITE, WVALID, WDATA, RREADY,
+    output  AREADY, WREADY, RVALID, RDATA
+  );
+
+endinterface