From 50b71c7f0ea2574eb4802e1a12fe8b0920a4ca7f Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 27 Apr 2024 12:14:41 -0600 Subject: rtl/axi_timer: initial commit This a buggy timer, imported from https://github.com/astrakhov-design/axi_timer. It will be used for a testbench hello world case --- rtl/axi_timer/axi_bus.sv | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 rtl/axi_timer/axi_bus.sv (limited to 'rtl/axi_timer/axi_bus.sv') diff --git a/rtl/axi_timer/axi_bus.sv b/rtl/axi_timer/axi_bus.sv new file mode 100644 index 0000000..f1460ca --- /dev/null +++ b/rtl/axi_timer/axi_bus.sv @@ -0,0 +1,28 @@ +//AXI interface bus +interface axi_bus #( + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 32 + ); + + logic [AXI_ADDR_WIDTH-1:0] ADDR; + logic AVALID; + logic AREADY; + logic AWRITE; + logic WVALID; + logic WREADY; + logic [AXI_DATA_WIDTH-1:0] WDATA; + logic RVALID; + logic RREADY; + logic [AXI_DATA_WIDTH-1:0] RDATA; + + modport Master( + input AREADY, WREADY, RVALID, RDATA, + output ADDR, AVALID, AWRITE, WVALID, WDATA, RREADY + ); + + modport Slave( + input ADDR, AVALID, AWRITE, WVALID, WDATA, RREADY, + output AREADY, WREADY, RVALID, RDATA + ); + +endinterface -- cgit v1.2.3