diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-05-03 12:01:36 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-03 12:01:36 -0600 |
| commit | d6dcfc10f26056485cb260af93027047a6aa8d30 (patch) | |
| tree | 358a7e69c13fe51f7348bba893c2489db9b022fc /platform/wavelet3d/gfx_sched.sv | |
| parent | 405c0287c80c34b0e9dfb9d9326b86d12433b4c4 (diff) | |
platform/wavelet3d: implement sched domain crossbar
Diffstat (limited to 'platform/wavelet3d/gfx_sched.sv')
| -rw-r--r-- | platform/wavelet3d/gfx_sched.sv | 32 |
1 files changed, 12 insertions, 20 deletions
diff --git a/platform/wavelet3d/gfx_sched.sv b/platform/wavelet3d/gfx_sched.sv index ebffd1a..b3cbc41 100644 --- a/platform/wavelet3d/gfx_sched.sv +++ b/platform/wavelet3d/gfx_sched.sv @@ -1,17 +1,17 @@ module gfx_sched +import gfx::*; ( - input logic clk, - rst_n, + input logic clk, + rst_n, + srst_n, - gfx_axil.m axim, - input gfx::irq_lines irq -); + gfx_axil.m axim, - import gfx::*; + input irq_lines irq +); logic axi_ready, axi_valid, bram_ready, bram_read, bram_write, bram_write_next, - mem_instr, mem_la_read, mem_la_write, mem_ready, mem_valid, - sync_rst_n, rst_done, select_bram; + mem_instr, mem_la_read, mem_la_write, mem_ready, mem_valid, select_bram; word bram[SCHED_BRAM_WORDS]; word axi_rdata, bram_rdata, mem_addr, mem_la_addr, mem_rdata, mem_wdata; @@ -22,7 +22,7 @@ module gfx_sched assign bram_addr = mem_addr[$bits(bram_addr) + SUBWORD_BITS - 1:SUBWORD_BITS]; assign mem_ready = (axi_valid & axi_ready) | bram_ready; assign mem_rdata = bram_ready ? bram_rdata : axi_rdata; - assign select_bram = ~|(mem_la_addr & ~((1 << ($bits(bram_addr) + SUBWORD_BITS)) - 1)); + assign select_bram = ~|mem_la_addr[$bits(mem_la_addr) - 1:$bits(bram_addr) + SUBWORD_BITS]; assign bram_write_next = mem_la_write & select_bram; defparam core.ENABLE_COUNTERS = 0; @@ -40,7 +40,7 @@ module gfx_sched picorv32 core ( .clk, - .resetn(sync_rst_n), + .resetn(srst_n), .trap(), .mem_valid, @@ -77,7 +77,7 @@ module gfx_sched picorv32_axi_adapter axi ( .clk, - .resetn(sync_rst_n), + .resetn(srst_n), .mem_axi_awvalid(axim.awvalid), .mem_axi_awready(axim.awready), @@ -123,20 +123,12 @@ module gfx_sched always_ff @(posedge clk or negedge rst_n) - if (!rst_n) begin - rst_done <= 0; - sync_rst_n <= 0; - + if (~rst_n) begin axi_valid <= 0; bram_read <= 0; bram_ready <= 0; bram_write <= 0; end else begin - if (rst_done) - sync_rst_n <= 1; - else - rst_done <= 1; - axi_valid <= ~select_bram | (axi_valid & ~axi_ready); bram_read <= mem_la_read & select_bram; bram_write <= bram_write_next; |