diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-10-03 07:45:12 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-03 07:45:26 -0600 |
| commit | f422a5fd9e83c69d4158a165edc47f45bcf600c4 (patch) | |
| tree | 8a00b06832eefeba28add6db77b4b486cdfe4767 /cache_hw.tcl | |
| parent | 6ddd97b7289b043c41ac65ae35931bd5b5acfaeb (diff) | |
rtl/cache: implement ll/sc line monitor
Diffstat (limited to 'cache_hw.tcl')
| -rw-r--r-- | cache_hw.tcl | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/cache_hw.tcl b/cache_hw.tcl index 4a06546..31aa5af 100644 --- a/cache_hw.tcl +++ b/cache_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Mon Oct 02 07:43:58 GMT 2023 +# Tue Oct 03 10:41:50 GMT 2023 # DO NOT MODIFY # # cache "8KiB 1-way cache w/ controller" v1.0 -# 2023.10.02.07:43:58 +# 2023.10.03.10:41:50 # # @@ -45,6 +45,7 @@ add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv add_fileset_file sram.sv SYSTEM_VERILOG PATH rtl/cache/sram.sv +add_fileset_file monitor.sv SYSTEM_VERILOG PATH rtl/cache/monitor.sv # |