From f422a5fd9e83c69d4158a165edc47f45bcf600c4 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 3 Oct 2023 07:45:12 -0600 Subject: rtl/cache: implement ll/sc line monitor --- cache_hw.tcl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'cache_hw.tcl') diff --git a/cache_hw.tcl b/cache_hw.tcl index 4a06546..31aa5af 100644 --- a/cache_hw.tcl +++ b/cache_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Mon Oct 02 07:43:58 GMT 2023 +# Tue Oct 03 10:41:50 GMT 2023 # DO NOT MODIFY # # cache "8KiB 1-way cache w/ controller" v1.0 -# 2023.10.02.07:43:58 +# 2023.10.03.10:41:50 # # @@ -45,6 +45,7 @@ add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv add_fileset_file sram.sv SYSTEM_VERILOG PATH rtl/cache/sram.sv +add_fileset_file monitor.sv SYSTEM_VERILOG PATH rtl/cache/monitor.sv # -- cgit v1.2.3