diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-01-21 06:23:46 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-02-20 11:11:17 -0600 |
| commit | f3b18ead59ae02f95dabbf0a1dea40873a816975 (patch) | |
| tree | 8979e50f2a37f66a4cd27e937b480efe60d72cf7 /cache_hw.tcl | |
| parent | a8bc5a353ea997f73209b39377ee15a73e471237 (diff) | |
rtl: refactor filenames and directory hierarchy
Diffstat (limited to 'cache_hw.tcl')
| -rw-r--r-- | cache_hw.tcl | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/cache_hw.tcl b/cache_hw.tcl index 712cf67..57b68e6 100644 --- a/cache_hw.tcl +++ b/cache_hw.tcl @@ -39,16 +39,16 @@ add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL cache set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/cache/cache.sv TOP_LEVEL_FILE add_fileset_file cache_control.sv SYSTEM_VERILOG PATH rtl/cache/cache_control.sv -add_fileset_file token.sv SYSTEM_VERILOG PATH rtl/cache/token.sv -add_fileset_file ring.sv SYSTEM_VERILOG PATH rtl/cache/ring.sv -add_fileset_file mem.sv SYSTEM_VERILOG PATH rtl/cache/mem.sv -add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv -add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv -add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv -add_fileset_file sram.sv SYSTEM_VERILOG PATH rtl/cache/sram.sv -add_fileset_file monitor.sv SYSTEM_VERILOG PATH rtl/cache/monitor.sv +add_fileset_file cache_token.sv SYSTEM_VERILOG PATH rtl/cache/cache_token.sv +add_fileset_file cache_ring.sv SYSTEM_VERILOG PATH rtl/cache/cache_ring.sv +add_fileset_file cache_mem.sv SYSTEM_VERILOG PATH rtl/cache/cache_mem.sv +add_fileset_file cache_offsets.sv SYSTEM_VERILOG PATH rtl/cache/cache_offsets.sv +add_fileset_file cache_routing.sv SYSTEM_VERILOG PATH rtl/cache/cache_routing.sv +add_fileset_file cache_sram.sv SYSTEM_VERILOG PATH rtl/cache/cache_sram.sv +add_fileset_file cache_monitor.sv SYSTEM_VERILOG PATH rtl/cache/cache_monitor.sv add_fileset_file cache_debug.sv SYSTEM_VERILOG PATH rtl/cache/cache_debug.sv |