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authorAlejandro Soto <alejandro@34project.org>2023-10-31 17:52:27 -0600
committerAlejandro Soto <alejandro@34project.org>2023-11-02 22:20:23 -0600
commit814eb9d024a928380815a8a830eee3b86d71cf75 (patch)
tree3fe80bd9dd5aabe1d944fe24935d2f2c2fb239e3
parenteed877444f9af85d6e4596853d8f188e61f6c4ed (diff)
ip: add ip_fp_inv
Diffstat
-rw-r--r--conspiracion.qsf4
-rw-r--r--gfx_hw.tcl1
-rw-r--r--ip/ip_fp_inv.cmp10
-rw-r--r--ip/ip_fp_inv.qip86
-rw-r--r--ip/ip_fp_inv.sip6
-rw-r--r--ip/ip_fp_inv.spd6
-rw-r--r--ip/ip_fp_inv.v92
-rw-r--r--ip/ip_fp_inv/dspba_library.vhd377
-rw-r--r--ip/ip_fp_inv/dspba_library_package.vhd72
-rw-r--r--ip/ip_fp_inv/ip_fp_inv_0002.vhd679
-rw-r--r--ip/ip_fp_inv_sim.f1
-rw-r--r--ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl278
-rw-r--r--ip/ip_fp_inv_sim/cadence/cds.lib19
-rw-r--r--ip/ip_fp_inv_sim/cadence/hdl.var2
-rwxr-xr-xip/ip_fp_inv_sim/cadence/ncsim_setup.sh195
-rw-r--r--ip/ip_fp_inv_sim/ip_fp_inv.vo862
-rw-r--r--ip/ip_fp_inv_sim/mentor/msim_setup.tcl272
-rwxr-xr-xip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh152
-rw-r--r--ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup13
-rwxr-xr-xip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh195
-rw-r--r--rtl/gfx/fp_add.sv2
-rw-r--r--rtl/gfx/fp_inv.sv36
-rw-r--r--rtl/gfx/fp_mul.sv2
-rw-r--r--rtl/gfx/gfx_defs.sv1
-rw-r--r--tb/verilator.hpp9
25 files changed, 3369 insertions, 3 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf
index f24575e..926b9b9 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -323,4 +323,6 @@ set_global_assignment -name SIP_FILE ip/ip_fp_mul.sip
set_global_assignment -name QIP_FILE ip/ip_fp_add.qip
set_global_assignment -name SIP_FILE ip/ip_fp_add.sip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name QIP_FILE ip/ip_fp_inv.qip
+set_global_assignment -name SIP_FILE ip/ip_fp_inv.sip \ No newline at end of file
diff --git a/gfx_hw.tcl b/gfx_hw.tcl
index 85f6155..15136f8 100644
--- a/gfx_hw.tcl
+++ b/gfx_hw.tcl
@@ -41,6 +41,7 @@ set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file gfx.sv SYSTEM_VERILOG PATH rtl/gfx/gfx.sv TOP_LEVEL_FILE
add_fileset_file fp_add.sv SYSTEM_VERILOG PATH rtl/gfx/fp_add.sv
+add_fileset_file fp_inv.sv SYSTEM_VERILOG PATH rtl/gfx/fp_inv.sv
add_fileset_file fp_mul.sv SYSTEM_VERILOG PATH rtl/gfx/fp_mul.sv
add_fileset_file gfx_cmd.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_cmd.sv
add_fileset_file gfx_defs.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_defs.sv
diff --git a/ip/ip_fp_inv.cmp b/ip/ip_fp_inv.cmp
new file mode 100644
index 0000000..a2cef51
--- /dev/null
+++ b/ip/ip_fp_inv.cmp
@@ -0,0 +1,10 @@
+ component ip_fp_inv is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ areset : in std_logic := 'X'; -- reset
+ en : in std_logic_vector(0 downto 0) := (others => 'X'); -- en
+ a : in std_logic_vector(15 downto 0) := (others => 'X'); -- a
+ q : out std_logic_vector(15 downto 0) -- q
+ );
+ end component ip_fp_inv;
+
diff --git a/ip/ip_fp_inv.qip b/ip/ip_fp_inv.qip
new file mode 100644
index 0000000..2f0ccac
--- /dev/null
+++ b/ip/ip_fp_inv.qip
@@ -0,0 +1,86 @@
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_TOOL_NAME "altera_fp_functions"
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "ip_fp_inv" -name MISC_FILE [file join $::quartus(qip_path) "ip_fp_inv.cmp"]
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_COMPONENT_NAME "aXBfZnBfaW52"
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_COMPONENT_DISPLAY_NAME "RlBfRlVOQ1RJT05TIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "ip_fp_inv" -library "ip_fp_inv" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_NAME "aXBfZnBfaW52XzAwMDI="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_DISPLAY_NAME "RlBfRlVOQ1RJT05TIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05fRkFNSUxZ::QVJJVEg=::RmFtaWx5"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "QVJJVEhfZnVuY3Rpb24=::SU5W::TmFtZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "Q09OVkVSVF9mdW5jdGlvbg==::RlhQX0ZQ::TmFtZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "QUxMX2Z1bmN0aW9u::QURE::TmFtZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "RVhQX0xPR19mdW5jdGlvbg==::RVhQRQ==::TmFtZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "VFJJR19mdW5jdGlvbg==::U0lO::TmFtZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "Q09NUEFSRV9mdW5jdGlvbg==::TUlO::TmFtZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "Uk9PVFNfZnVuY3Rpb24=::U1FSVA==::TmFtZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZGZ1bmN0aW9u::SU5W::ZGVyaXZlZGZ1bmN0aW9u"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::Y3VzdG9t::Rm9ybWF0"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::NQ==::RXhwb25lbnQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::NQ==::ZnBfZXhwX2Rlcml2ZWQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MTA=::TWFudGlzc2E="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MTA=::ZnBfbWFuX2Rlcml2ZWQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MjAw::VGFyZ2V0"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Mg==::VGFyZ2V0"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::ZnJlcXVlbmN5::R29hbA=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "dXNlX3JvdW5kaW5nX21vZGU=::dHJ1ZQ==::dXNlX3JvdW5kaW5nX21vZGU="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZmFpdGhmdWxfcm91bmRpbmc=::dHJ1ZQ==::UmVsYXggcm91bmRpbmcgdG8gcm91bmQgdXAgb3IgZG93biB0byByZWR1Y2UgcmVzb3VyY2UgdXNhZ2U="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::dHJ1ZQ==::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZGl2aWRlX3R5cGU=::MA==::TWV0aG9k"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "c2VsZWN0X3NpZ25hbF9lbmFibGU=::ZmFsc2U=::VXNlIFNlbGVjdCBTaWduYWw="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "c2NhbGVfYnlfcGk=::ZmFsc2U=::UmVwcmVzZW50IGFuZ2xlIGFzIG11bHRpcGxlIG9mIFBp"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2lucHV0cw==::Mg==::SW5wdXQgVmVjdG9yIERpbWVuc2lvbg=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "dHJpZ19ub19yYW5nZV9yZWR1Y3Rpb24=::ZmFsc2U=::SW5wdXRzIGFyZSB3aXRoaW4gcmFuZ2UgLTJwaSB0byArMnBp"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "cmVwb3J0X3Jlc291cmNlc190b194bWw=::ZmFsc2U=::cmVwb3J0X3Jlc291cmNlc190b194bWw="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::Mw==::bGF0ZW5jeV9mZWVkYmFjaw=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cF9kZXJpdmVk::OA==::ZnBfb3V0X2V4cF9kZXJpdmVk"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbg==::MjM=::T3V0cHV0IE1hbnRpc3Nh"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbl9kZXJpdmVk::OA==::ZnBfb3V0X21hbl9kZXJpdmVk"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZm9ybWF0::c2luZ2xl::SW5wdXQgRm9ybWF0"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhw::OA==::SW5wdXQgRXhwb25lbnQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhwX2Rlcml2ZWQ=::OA==::ZnBfaW5fZXhwX2Rlcml2ZWQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFu::MjM=::SW5wdXQgTWFudGlzc2E="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFuX2Rlcml2ZWQ=::OA==::ZnBfaW5fbWFuX2Rlcml2ZWQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2hhcmRfZnA=::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MQ==::TXVsdGlwbGllcw=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MTc4::TFVUcw=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ=="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=::Nw==::c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU="
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_COMPONENT_PARAMETER "dmFsaWRhdGlvbl9mYWlsZWQ=::ZmFsc2U=::dmFsaWRhdGlvbl9mYWlsZWQ="
+
+set_global_assignment -library "ip_fp_inv" -name VERILOG_FILE [file join $::quartus(qip_path) "ip_fp_inv.v"]
+set_global_assignment -library "ip_fp_inv" -name VHDL_FILE [file join $::quartus(qip_path) "ip_fp_inv/dspba_library_package.vhd"]
+set_global_assignment -library "ip_fp_inv" -name VHDL_FILE [file join $::quartus(qip_path) "ip_fp_inv/dspba_library.vhd"]
+set_global_assignment -library "ip_fp_inv" -name VHDL_FILE [file join $::quartus(qip_path) "ip_fp_inv/ip_fp_inv_0002.vhd"]
+
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_TOOL_NAME "altera_fp_functions"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "ip_fp_inv_0002" -library "ip_fp_inv" -name IP_TOOL_ENV "mwpim"
diff --git a/ip/ip_fp_inv.sip b/ip/ip_fp_inv.sip
new file mode 100644
index 0000000..46518c7
--- /dev/null
+++ b/ip/ip_fp_inv.sip
@@ -0,0 +1,6 @@
+set_global_assignment -entity "ip_fp_inv" -library "lib_ip_fp_inv" -name IP_TOOL_NAME "altera_fp_functions"
+set_global_assignment -entity "ip_fp_inv" -library "lib_ip_fp_inv" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "ip_fp_inv" -library "lib_ip_fp_inv" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_ip_fp_inv" -name SPD_FILE [file join $::quartus(sip_path) "ip_fp_inv.spd"]
+
+set_global_assignment -library "lib_ip_fp_inv" -name MISC_FILE [file join $::quartus(sip_path) "ip_fp_inv_sim/ip_fp_inv.vo"]
diff --git a/ip/ip_fp_inv.spd b/ip/ip_fp_inv.spd
new file mode 100644
index 0000000..998a206
--- /dev/null
+++ b/ip/ip_fp_inv.spd
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file path="ip_fp_inv_sim/ip_fp_inv.vo" type="VERILOG" />
+ <topLevel name="ip_fp_inv" />
+ <deviceFamily name="cyclonev" />
+</simPackage>
diff --git a/ip/ip_fp_inv.v b/ip/ip_fp_inv.v
new file mode 100644
index 0000000..047b334
--- /dev/null
+++ b/ip/ip_fp_inv.v
@@ -0,0 +1,92 @@
+// megafunction wizard: %FP_FUNCTIONS Intel FPGA IP v20.1%
+// GENERATION: XML
+// ip_fp_inv.v
+
+// Generated using ACDS version 20.1 720
+
+`timescale 1 ps / 1 ps
+module ip_fp_inv (
+ input wire clk, // clk.clk
+ input wire areset, // areset.reset
+ input wire [0:0] en, // en.en
+ input wire [15:0] a, // a.a
+ output wire [15:0] q // q.q
+ );
+
+ ip_fp_inv_0002 ip_fp_inv_inst (
+ .clk (clk), // clk.clk
+ .areset (areset), // areset.reset
+ .en (en), // en.en
+ .a (a), // a.a
+ .q (q) // q.q
+ );
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+// Generated by Altera MegaWizard Launcher Utility version 1.0
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+// Copyright (C) 1991-2023 Altera Corporation
+// Any megafunction design, and related net list (encrypted or decrypted),
+// support information, device programming or simulation file, and any other
+// associated documentation or information provided by Altera or a partner
+// under Altera's Megafunction Partnership Program may be used only to
+// program PLD devices (but not masked PLD devices) from Altera. Any other
+// use of such megafunction design, net list, support information, device
+// programming or simulation file, or any other related documentation or
+// information is prohibited for any other purpose, including, but not
+// limited to modification, reverse engineering, de-compiling, or use with
+// any other silicon devices, unless such use is explicitly licensed under
+// a separate agreement with Altera or a megafunction partner. Title to
+// the intellectual property, including patents, copyrights, trademarks,
+// trade secrets, or maskworks, embodied in any such megafunction design,
+// net list, support information, device programming or simulation file, or
+// any other related documentation or information provided by Altera or a
+// megafunction partner, remains with Altera, the megafunction partner, or
+// their respective licensors. No other licenses, including any licenses
+// needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_fp_functions" version="20.1" >
+// Retrieval info: <generic name="FUNCTION_FAMILY" value="ARITH" />
+// Retrieval info: <generic name="ARITH_function" value="INV" />
+// Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
+// Retrieval info: <generic name="ALL_function" value="ADD" />
+// Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
+// Retrieval info: <generic name="TRIG_function" value="SIN" />
+// Retrieval info: <generic name="COMPARE_function" value="MIN" />
+// Retrieval info: <generic name="ROOTS_function" value="SQRT" />
+// Retrieval info: <generic name="fp_format" value="custom" />
+// Retrieval info: <generic name="fp_exp" value="5" />
+// Retrieval info: <generic name="fp_man" value="10" />
+// Retrieval info: <generic name="exponent_width" value="23" />
+// Retrieval info: <generic name="frequency_target" value="200" />
+// Retrieval info: <generic name="latency_target" value="2" />
+// Retrieval info: <generic name="performance_goal" value="frequency" />
+// Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
+// Retrieval info: <generic name="faithful_rounding" value="true" />
+// Retrieval info: <generic name="gen_enable" value="true" />
+// Retrieval info: <generic name="divide_type" value="0" />
+// Retrieval info: <generic name="select_signal_enable" value="false" />
+// Retrieval info: <generic name="scale_by_pi" value="false" />
+// Retrieval info: <generic name="number_of_inputs" value="2" />
+// Retrieval info: <generic name="trig_no_range_reduction" value="false" />
+// Retrieval info: <generic name="report_resources_to_xml" value="false" />
+// Retrieval info: <generic name="fxpt_width" value="32" />
+// Retrieval info: <generic name="fxpt_fraction" value="0" />
+// Retrieval info: <generic name="fxpt_sign" value="1" />
+// Retrieval info: <generic name="fp_out_format" value="single" />
+// Retrieval info: <generic name="fp_out_exp" value="8" />
+// Retrieval info: <generic name="fp_out_man" value="23" />
+// Retrieval info: <generic name="fp_in_format" value="single" />
+// Retrieval info: <generic name="fp_in_exp" value="8" />
+// Retrieval info: <generic name="fp_in_man" value="23" />
+// Retrieval info: <generic name="enable_hard_fp" value="true" />
+// Retrieval info: <generic name="manual_dsp_planning" value="true" />
+// Retrieval info: <generic name="forceRegisters" value="1111" />
+// Retrieval info: <generic name="selected_device_family" value="Cyclone V" />
+// Retrieval info: <generic name="selected_device_speedgrade" value="7" />
+// Retrieval info: </instance>
+// IPFS_FILES : ip_fp_inv.vo
+// RELATED_FILES: ip_fp_inv.v, dspba_library_package.vhd, dspba_library.vhd, ip_fp_inv_0002.vhd
diff --git a/ip/ip_fp_inv/dspba_library.vhd b/ip/ip_fp_inv/dspba_library.vhd
new file mode 100644
index 0000000..c38c661
--- /dev/null
+++ b/ip/ip_fp_inv/dspba_library.vhd
@@ -0,0 +1,377 @@
+-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files any of the foregoing device programming or simulation files), and
+-- any associated documentation or information are expressly subject to the
+-- terms and conditions of the Intel FPGA Software License Agreement,
+-- Intel MegaCore Function License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for the sole
+-- purpose of programming logic devices manufactured by Intel and sold by
+-- Intel or its authorized distributors. Please refer to the applicable
+-- agreement for further details.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use work.dspba_library_package.all;
+
+entity dspba_delay is
+ generic (
+ width : natural := 8;
+ depth : natural := 1;
+ reset_high : std_logic := '1';
+ reset_kind : string := "ASYNC"
+ );
+ port (
+ clk : in std_logic;
+ aclr : in std_logic;
+ ena : in std_logic := '1';
+ xin : in std_logic_vector(width-1 downto 0);
+ xout : out std_logic_vector(width-1 downto 0)
+ );
+end dspba_delay;
+
+architecture delay of dspba_delay is
+ type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
+ signal delay_signals : delay_array;
+begin
+ delay_signals(depth) <= xin;
+
+ delay_block: if 0 < depth generate
+ begin
+ delay_loop: for i in depth-1 downto 0 generate
+ begin
+ async_reset: if reset_kind = "ASYNC" generate
+ process(clk, aclr)
+ begin
+ if aclr=reset_high then
+ delay_signals(i) <= (others => '0');
+ elsif clk'event and clk='1' then
+ if ena='1' then
+ delay_signals(i) <= delay_signals(i + 1);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ sync_reset: if reset_kind = "SYNC" generate
+ process(clk)
+ begin
+ if clk'event and clk='1' then
+ if aclr=reset_high then
+ delay_signals(i) <= (others => '0');
+ elsif ena='1' then
+ delay_signals(i) <= delay_signals(i + 1);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ no_reset: if reset_kind = "NONE" generate
+ process(clk)
+ begin
+ if clk'event and clk='1' then
+ if ena='1' then
+ delay_signals(i) <= delay_signals(i + 1);
+ end if;
+ end if;
+ end process;
+ end generate;
+ end generate;
+ end generate;
+
+ xout <= delay_signals(0);
+end delay;
+
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.dspba_library_package.all;
+
+entity dspba_sync_reg is
+ generic (
+ width1 : natural := 8;
+ init_value : std_logic_vector;
+ width2 : natural := 8;
+ depth : natural := 2;
+ pulse_multiplier : natural := 1;
+ counter_width : natural := 8;
+ reset1_high : std_logic := '1';
+ reset2_high : std_logic := '1';
+ reset_kind : string := "ASYNC"
+ );
+ port (
+ clk1 : in std_logic;
+ aclr1 : in std_logic;
+ ena : in std_logic_vector(0 downto 0);
+ xin : in std_logic_vector(width1-1 downto 0);
+ xout : out std_logic_vector(width1-1 downto 0);
+ clk2 : in std_logic;
+ aclr2 : in std_logic;
+ sxout : out std_logic_vector(width2-1 downto 0)
+ );
+end entity;
+
+architecture sync_reg of dspba_sync_reg is
+ type bit_array is array (depth-1 downto 0) of std_logic;
+
+ signal iclk_enable : std_logic;
+ signal iclk_data : std_logic_vector(width1-1 downto 0);
+ signal oclk_data : std_logic_vector(width2-1 downto 0);
+
+ -- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
+ -- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis
+ signal sync_regs : bit_array;
+ attribute altera_attribute : string;
+ attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
+
+ signal oclk_enable : std_logic;
+
+ constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
+
+ signal counter : UNSIGNED(counter_width-1 downto 0);
+ signal ena_internal : std_logic;
+begin
+ oclk_enable <= sync_regs(depth-1);
+
+ no_multiplication: if pulse_multiplier=1 generate
+ ena_internal <= ena(0);
+ end generate;
+
+ async_reset: if reset_kind="ASYNC" generate
+
+ multiply_ena: if pulse_multiplier>1 generate
+ ena_internal <= '1' when counter>0 else ena(0);
+ process (clk1, aclr1)
+ begin
+ if aclr1=reset1_high then
+ counter <= (others => '0');
+ elsif clk1'event and clk1='1' then
+ if counter>0 then
+ if counter=pulse_multiplier-1 then
+ counter <= (others => '0');
+ else
+ counter <= counter + TO_UNSIGNED(1, counter_width);
+ end if;
+ else
+ if ena(0)='1' then
+ counter <= TO_UNSIGNED(1, counter_width);
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk1, aclr1)
+ begin
+ if aclr1=reset1_high then
+ iclk_enable <= '0';
+ iclk_data <= init_value_internal;
+ elsif clk1'event and clk1='1' then
+ iclk_enable <= ena_internal;
+ if ena(0)='1' then
+ iclk_data <= xin;
+ end if;
+ end if;
+ end process;
+
+ sync_reg_loop: for i in 0 to depth-1 generate
+ process (clk2, aclr2)
+ begin
+ if aclr2=reset2_high then
+ sync_regs(i) <= '0';
+ elsif clk2'event and clk2='1' then
+ if i>0 then
+ sync_regs(i) <= sync_regs(i-1);
+ else
+ sync_regs(i) <= iclk_enable;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk2, aclr2)
+ begin
+ if aclr2=reset2_high then
+ oclk_data <= init_value_internal(width2-1 downto 0);
+ elsif clk2'event and clk2='1' then
+ if oclk_enable='1' then
+ oclk_data <= iclk_data(width2-1 downto 0);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ sync_reset: if reset_kind="SYNC" generate
+
+ multiply_ena: if pulse_multiplier>1 generate
+ ena_internal <= '1' when counter>0 else ena(0);
+ process (clk1)
+ begin
+ if clk1'event and clk1='1' then
+ if aclr1=reset1_high then
+ counter <= (others => '0');
+ else
+ if counter>0 then
+ if counter=pulse_multiplier-1 then
+ counter <= (others => '0');
+ else
+ counter <= counter + TO_UNSIGNED(1, counter_width);
+ end if;
+ else
+ if ena(0)='1' then
+ counter <= TO_UNSIGNED(1, counter_width);
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk1)
+ begin
+ if clk1'event and clk1='1' then
+ if aclr1=reset1_high then
+ iclk_enable <= '0';
+ iclk_data <= init_value_internal;
+ else
+ iclk_enable <= ena_internal;
+ if ena(0)='1' then
+ iclk_data <= xin;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ sync_reg_loop: for i in 0 to depth-1 generate
+ process (clk2)
+ begin
+ if clk2'event and clk2='1' then
+ if aclr2=reset2_high then
+ sync_regs(i) <= '0';
+ else
+ if i>0 then
+ sync_regs(i) <= sync_regs(i-1);
+ else
+ sync_regs(i) <= iclk_enable;
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk2)
+ begin
+ if clk2'event and clk2='1' then
+ if aclr2=reset2_high then
+ oclk_data <= init_value_internal(width2-1 downto 0);
+ elsif oclk_enable='1' then
+ oclk_data <= iclk_data(width2-1 downto 0);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ none_reset: if reset_kind="NONE" generate
+
+ multiply_ena: if pulse_multiplier>1 generate
+ ena_internal <= '1' when counter>0 else ena(0);
+ process (clk1, aclr1)
+ begin
+ if clk1'event and clk1='1' then
+ if counter>0 then
+ if counter=pulse_multiplier-1 then
+ counter <= (others => '0');
+ else
+ counter <= counter + TO_UNSIGNED(1, counter_width);
+ end if;
+ else
+ if ena(0)='1' then
+ counter <= TO_UNSIGNED(1, counter_width);
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk1)
+ begin
+ if clk1'event and clk1='1' then
+ iclk_enable <= ena_internal;
+ if ena(0)='1' then
+ iclk_data <= xin;
+ end if;
+ end if;
+ end process;
+
+ sync_reg_loop: for i in 0 to depth-1 generate
+ process (clk2)
+ begin
+ if clk2'event and clk2='1' then
+ if i>0 then
+ sync_regs(i) <= sync_regs(i-1);
+ else
+ sync_regs(i) <= iclk_enable;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk2)
+ begin
+ if clk2'event and clk2='1' then
+ if oclk_enable='1' then
+ oclk_data <= iclk_data(width2-1 downto 0);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ xout <= iclk_data;
+ sxout <= oclk_data;
+
+end sync_reg;
+
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dspba_pipe is
+ generic(
+ num_bits : positive := 8;
+ num_stages : natural := 0;
+ init_value : std_logic := 'X'
+ );
+ port(
+ clk: in std_logic;
+ d : in std_logic_vector(num_bits-1 downto 0);
+ q : out std_logic_vector(num_bits-1 downto 0)
+ );
+end entity dspba_pipe;
+
+architecture rtl of dspba_pipe is
+ attribute altera_attribute : string;
+ attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off";
+
+ type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0);
+ signal stage_array : stage_array_type := (others => (others => init_value));
+begin
+ stage_array(0) <= d;
+
+ g_pipe : for i in 1 to num_stages generate
+ p_stage : process (clk) is
+ begin
+ if rising_edge(clk) then
+ stage_array(i) <= stage_array(i-1);
+ end if;
+ end process p_stage;
+ end generate g_pipe;
+
+ q <= stage_array(num_stages);
+
+end rtl;
+
diff --git a/ip/ip_fp_inv/dspba_library_package.vhd b/ip/ip_fp_inv/dspba_library_package.vhd
new file mode 100644
index 0000000..d03bca8
--- /dev/null
+++ b/ip/ip_fp_inv/dspba_library_package.vhd
@@ -0,0 +1,72 @@
+-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files any of the foregoing device programming or simulation files), and
+-- any associated documentation or information are expressly subject to the
+-- terms and conditions of the Intel FPGA Software License Agreement,
+-- Intel MegaCore Function License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for the sole
+-- purpose of programming logic devices manufactured by Intel and sold by
+-- Intel or its authorized distributors. Please refer to the applicable
+-- agreement for further details.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package dspba_library_package is
+
+ component dspba_delay is
+ generic (
+ width : natural := 8;
+ depth : natural := 1;
+ reset_high : std_logic := '1';
+ reset_kind : string := "ASYNC"
+ );
+ port (
+ clk : in std_logic;
+ aclr : in std_logic;
+ ena : in std_logic := '1';
+ xin : in std_logic_vector(width-1 downto 0);
+ xout : out std_logic_vector(width-1 downto 0)
+ );
+ end component;
+
+ component dspba_sync_reg is
+ generic (
+ width1 : natural := 8;
+ width2 : natural := 8;
+ depth : natural := 2;
+ init_value : std_logic_vector;
+ pulse_multiplier : natural := 1;
+ counter_width : natural := 8;
+ reset1_high : std_logic := '1';
+ reset2_high : std_logic := '1';
+ reset_kind : string := "ASYNC"
+ );
+ port (
+ clk1 : in std_logic;
+ aclr1 : in std_logic;
+ ena : in std_logic_vector(0 downto 0);
+ xin : in std_logic_vector(width1-1 downto 0);
+ xout : out std_logic_vector(width1-1 downto 0);
+ clk2 : in std_logic;
+ aclr2 : in std_logic;
+ sxout : out std_logic_vector(width2-1 downto 0)
+ );
+ end component;
+
+ component dspba_pipe is
+ generic(
+ num_bits : positive;
+ num_stages : natural;
+ init_value : std_logic := 'X'
+ );
+ port(
+ clk: in std_logic;
+ d : in std_logic_vector(num_bits-1 downto 0);
+ q : out std_logic_vector(num_bits-1 downto 0)
+ );
+ end component dspba_pipe;
+
+end dspba_library_package;
diff --git a/ip/ip_fp_inv/ip_fp_inv_0002.vhd b/ip/ip_fp_inv/ip_fp_inv_0002.vhd
new file mode 100644
index 0000000..11f4aec
--- /dev/null
+++ b/ip/ip_fp_inv/ip_fp_inv_0002.vhd
@@ -0,0 +1,679 @@
+-- -------------------------------------------------------------------------
+-- High Level Design Compiler for Intel(R) FPGAs Version 20.1 (Release Build #720)
+-- Quartus Prime development tool and MATLAB/Simulink Interface
+--
+-- Legal Notice: Copyright 2020 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files any of the foregoing (including device programming or simulation
+-- files), and any associated documentation or information are expressly
+-- subject to the terms and conditions of the Intel FPGA Software License
+-- Agreement, Intel MegaCore Function License Agreement, or other applicable
+-- license agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by Intel
+-- and sold by Intel or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+-- ---------------------------------------------------------------------------
+
+-- VHDL created from ip_fp_inv_0002
+-- VHDL created on Tue Oct 31 07:43:54 2023
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+use IEEE.MATH_REAL.all;
+use std.TextIO.all;
+use work.dspba_library_package.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.altera_syncram;
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+entity ip_fp_inv_0002 is
+ port (
+ a : in std_logic_vector(15 downto 0); -- float16_m10
+ en : in std_logic_vector(0 downto 0); -- ufix1
+ q : out std_logic_vector(15 downto 0); -- float16_m10
+ clk : in std_logic;
+ areset : in std_logic
+ );
+end ip_fp_inv_0002;
+
+architecture normal of ip_fp_inv_0002 is
+
+ attribute altera_attribute : string;
+ attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
+
+ signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal expX_uid6_fpInverseTest_b : STD_LOGIC_VECTOR (4 downto 0);
+ signal fracX_uid7_fpInverseTest_b : STD_LOGIC_VECTOR (9 downto 0);
+ signal singX_uid8_fpInverseTest_b : STD_LOGIC_VECTOR (0 downto 0);
+ signal cstAllOWE_uid9_fpInverseTest_q : STD_LOGIC_VECTOR (4 downto 0);
+ signal cstAllZWF_uid10_fpInverseTest_q : STD_LOGIC_VECTOR (9 downto 0);
+ signal cstNaNWF_uid11_fpInverseTest_q : STD_LOGIC_VECTOR (9 downto 0);
+ signal cstAllZWE_uid12_fpInverseTest_q : STD_LOGIC_VECTOR (4 downto 0);
+ signal cst2BiasM1_uid13_fpInverseTest_q : STD_LOGIC_VECTOR (4 downto 0);
+ signal cst2Bias_uid14_fpInverseTest_q : STD_LOGIC_VECTOR (4 downto 0);
+ signal excZ_x_uid21_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal expXIsMax_uid22_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsZero_uid23_fpInverseTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsZero_uid23_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsNotZero_uid24_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excI_x_uid25_fpInverseTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excI_x_uid25_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excN_x_uid26_fpInverseTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excN_x_uid26_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal invExpXIsMax_uid27_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal InvExpXIsZero_uid28_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excR_x_uid29_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal oFracX_uid30_fpInverseTest_q : STD_LOGIC_VECTOR (10 downto 0);
+ signal updatedY_uid32_fpInverseTest_q : STD_LOGIC_VECTOR (10 downto 0);
+ signal fracXIsZero_uid31_fpInverseTest_a : STD_LOGIC_VECTOR (10 downto 0);
+ signal fracXIsZero_uid31_fpInverseTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsZero_uid31_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal y_uid34_fpInverseTest_in : STD_LOGIC_VECTOR (9 downto 0);
+ signal y_uid34_fpInverseTest_b : STD_LOGIC_VECTOR (9 downto 0);
+ signal expRCompExt_uid39_fpInverseTest_a : STD_LOGIC_VECTOR (5 downto 0);
+ signal expRCompExt_uid39_fpInverseTest_b : STD_LOGIC_VECTOR (5 downto 0);
+ signal expRCompExt_uid39_fpInverseTest_o : STD_LOGIC_VECTOR (5 downto 0);
+ signal expRCompExt_uid39_fpInverseTest_q : STD_LOGIC_VECTOR (5 downto 0);
+ signal expRComp_uid40_fpInverseTest_in : STD_LOGIC_VECTOR (4 downto 0);
+ signal expRComp_uid40_fpInverseTest_b : STD_LOGIC_VECTOR (4 downto 0);
+ signal udf_uid41_fpInverseTest_in : STD_LOGIC_VECTOR (6 downto 0);
+ signal udf_uid41_fpInverseTest_b : STD_LOGIC_VECTOR (0 downto 0);
+ signal expRCompYIsOneExt_uid42_fpInverseTest_a : STD_LOGIC_VECTOR (5 downto 0);
+ signal expRCompYIsOneExt_uid42_fpInverseTest_b : STD_LOGIC_VECTOR (5 downto 0);
+ signal expRCompYIsOneExt_uid42_fpInverseTest_o : STD_LOGIC_VECTOR (5 downto 0);
+ signal expRCompYIsOneExt_uid42_fpInverseTest_q : STD_LOGIC_VECTOR (5 downto 0);
+ signal expRCompYIsOne_uid43_fpInverseTest_in : STD_LOGIC_VECTOR (4 downto 0);
+ signal expRCompYIsOne_uid43_fpInverseTest_b : STD_LOGIC_VECTOR (4 downto 0);
+ signal fxpInverseRes_uid44_fpInverseTest_in : STD_LOGIC_VECTOR (15 downto 0);
+ signal fxpInverseRes_uid44_fpInverseTest_b : STD_LOGIC_VECTOR (10 downto 0);
+ signal fxpInverseResFrac_uid46_fpInverseTest_in : STD_LOGIC_VECTOR (9 downto 0);
+ signal fxpInverseResFrac_uid46_fpInverseTest_b : STD_LOGIC_VECTOR (9 downto 0);
+ signal fracRCalc_uid47_fpInverseTest_s : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracRCalc_uid47_fpInverseTest_q : STD_LOGIC_VECTOR (9 downto 0);
+ signal expRCalc_uid48_fpInverseTest_s : STD_LOGIC_VECTOR (0 downto 0);
+ signal expRCalc_uid48_fpInverseTest_q : STD_LOGIC_VECTOR (4 downto 0);
+ signal xRegAndUdf_uid49_fpInverseTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal xRegAndUdf_uid49_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal xIOrXRUdf_uid50_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excSelBits_uid51_fpInverseTest_q : STD_LOGIC_VECTOR (2 downto 0);
+ signal outMuxSelEnc_uid52_fpInverseTest_q : STD_LOGIC_VECTOR (1 downto 0);
+ signal fracRPostExc_uid54_fpInverseTest_s : STD_LOGIC_VECTOR (1 downto 0);
+ signal fracRPostExc_uid54_fpInverseTest_q : STD_LOGIC_VECTOR (9 downto 0);
+ signal expRPostExc_uid55_fpInverseTest_s : STD_LOGIC_VECTOR (1 downto 0);
+ signal expRPostExc_uid55_fpInverseTest_q : STD_LOGIC_VECTOR (4 downto 0);
+ signal invExcRNaN_uid56_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal signR_uid57_fpInverseTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal R_uid58_fpInverseTest_q : STD_LOGIC_VECTOR (15 downto 0);
+ signal memoryC0_uid60_inverseTables_q : STD_LOGIC_VECTOR (9 downto 0);
+ signal memoryC0_uid61_inverseTables_q : STD_LOGIC_VECTOR (5 downto 0);
+ signal os_uid62_inverseTables_q : STD_LOGIC_VECTOR (15 downto 0);
+ signal memoryC1_uid64_inverseTables_q : STD_LOGIC_VECTOR (8 downto 0);
+ signal lowRangeB_uid71_invPolyEval_in : STD_LOGIC_VECTOR (1 downto 0);
+ signal lowRangeB_uid71_invPolyEval_b : STD_LOGIC_VECTOR (1 downto 0);
+ signal highBBits_uid72_invPolyEval_b : STD_LOGIC_VECTOR (8 downto 0);
+ signal s1sumAHighB_uid73_invPolyEval_a : STD_LOGIC_VECTOR (16 downto 0);
+ signal s1sumAHighB_uid73_invPolyEval_b : STD_LOGIC_VECTOR (16 downto 0);
+ signal s1sumAHighB_uid73_invPolyEval_o : STD_LOGIC_VECTOR (16 downto 0);
+ signal s1sumAHighB_uid73_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
+ signal s1_uid74_invPolyEval_q : STD_LOGIC_VECTOR (18 downto 0);
+ signal prodXY_uid76_pT1_uid70_invPolyEval_a0 : STD_LOGIC_VECTOR (3 downto 0);
+ signal prodXY_uid76_pT1_uid70_invPolyEval_b0 : STD_LOGIC_VECTOR (8 downto 0);
+ signal prodXY_uid76_pT1_uid70_invPolyEval_s1 : STD_LOGIC_VECTOR (12 downto 0);
+ signal prodXY_uid76_pT1_uid70_invPolyEval_pr : SIGNED (13 downto 0);
+ signal prodXY_uid76_pT1_uid70_invPolyEval_q : STD_LOGIC_VECTOR (12 downto 0);
+ signal osig_uid77_pT1_uid70_invPolyEval_b : STD_LOGIC_VECTOR (10 downto 0);
+ signal yAddr_uid36_fpInverseTest_merged_bit_select_b : STD_LOGIC_VECTOR (5 downto 0);
+ signal yAddr_uid36_fpInverseTest_merged_bit_select_c : STD_LOGIC_VECTOR (3 downto 0);
+ signal redist0_yAddr_uid36_fpInverseTest_merged_bit_select_b_1_q : STD_LOGIC_VECTOR (5 downto 0);
+ signal redist1_fxpInverseResFrac_uid46_fpInverseTest_b_1_q : STD_LOGIC_VECTOR (9 downto 0);
+ signal redist2_fracXIsZero_uid31_fpInverseTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist3_fracXIsZero_uid31_fpInverseTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist4_fracXIsZero_uid23_fpInverseTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist5_excZ_x_uid21_fpInverseTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist6_singX_uid8_fpInverseTest_b_3_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist7_expX_uid6_fpInverseTest_b_2_q : STD_LOGIC_VECTOR (4 downto 0);
+
+begin
+
+
+ -- fracX_uid7_fpInverseTest(BITSELECT,6)@0
+ fracX_uid7_fpInverseTest_b <= a(9 downto 0);
+
+ -- cstAllZWF_uid10_fpInverseTest(CONSTANT,9)
+ cstAllZWF_uid10_fpInverseTest_q <= "0000000000";
+
+ -- fracXIsZero_uid23_fpInverseTest(LOGICAL,22)@0 + 1
+ fracXIsZero_uid23_fpInverseTest_qi <= "1" WHEN cstAllZWF_uid10_fpInverseTest_q = fracX_uid7_fpInverseTest_b ELSE "0";
+ fracXIsZero_uid23_fpInverseTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsZero_uid23_fpInverseTest_qi, xout => fracXIsZero_uid23_fpInverseTest_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- redist4_fracXIsZero_uid23_fpInverseTest_q_2(DELAY,83)
+ redist4_fracXIsZero_uid23_fpInverseTest_q_2 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsZero_uid23_fpInverseTest_q, xout => redist4_fracXIsZero_uid23_fpInverseTest_q_2_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- fracXIsNotZero_uid24_fpInverseTest(LOGICAL,23)@2
+ fracXIsNotZero_uid24_fpInverseTest_q <= not (redist4_fracXIsZero_uid23_fpInverseTest_q_2_q);
+
+ -- cstAllOWE_uid9_fpInverseTest(CONSTANT,8)
+ cstAllOWE_uid9_fpInverseTest_q <= "11111";
+
+ -- expX_uid6_fpInverseTest(BITSELECT,5)@0
+ expX_uid6_fpInverseTest_b <= a(14 downto 10);
+
+ -- redist7_expX_uid6_fpInverseTest_b_2(DELAY,86)
+ redist7_expX_uid6_fpInverseTest_b_2 : dspba_delay
+ GENERIC MAP ( width => 5, depth => 2, reset_kind => "ASYNC" )
+ PORT MAP ( xin => expX_uid6_fpInverseTest_b, xout => redist7_expX_uid6_fpInverseTest_b_2_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- expXIsMax_uid22_fpInverseTest(LOGICAL,21)@2
+ expXIsMax_uid22_fpInverseTest_q <= "1" WHEN redist7_expX_uid6_fpInverseTest_b_2_q = cstAllOWE_uid9_fpInverseTest_q ELSE "0";
+
+ -- excN_x_uid26_fpInverseTest(LOGICAL,25)@2 + 1
+ excN_x_uid26_fpInverseTest_qi <= expXIsMax_uid22_fpInverseTest_q and fracXIsNotZero_uid24_fpInverseTest_q;
+ excN_x_uid26_fpInverseTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excN_x_uid26_fpInverseTest_qi, xout => excN_x_uid26_fpInverseTest_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- invExcRNaN_uid56_fpInverseTest(LOGICAL,55)@3
+ invExcRNaN_uid56_fpInverseTest_q <= not (excN_x_uid26_fpInverseTest_q);
+
+ -- singX_uid8_fpInverseTest(BITSELECT,7)@0
+ singX_uid8_fpInverseTest_b <= STD_LOGIC_VECTOR(a(15 downto 15));
+
+ -- redist6_singX_uid8_fpInverseTest_b_3(DELAY,85)
+ redist6_singX_uid8_fpInverseTest_b_3 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
+ PORT MAP ( xin => singX_uid8_fpInverseTest_b, xout => redist6_singX_uid8_fpInverseTest_b_3_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- signR_uid57_fpInverseTest(LOGICAL,56)@3
+ signR_uid57_fpInverseTest_q <= redist6_singX_uid8_fpInverseTest_b_3_q and invExcRNaN_uid56_fpInverseTest_q;
+
+ -- cst2Bias_uid14_fpInverseTest(CONSTANT,13)
+ cst2Bias_uid14_fpInverseTest_q <= "11110";
+
+ -- expRCompYIsOneExt_uid42_fpInverseTest(SUB,41)@2
+ expRCompYIsOneExt_uid42_fpInverseTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid14_fpInverseTest_q);
+ expRCompYIsOneExt_uid42_fpInverseTest_b <= STD_LOGIC_VECTOR("0" & redist7_expX_uid6_fpInverseTest_b_2_q);
+ expRCompYIsOneExt_uid42_fpInverseTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid42_fpInverseTest_a) - UNSIGNED(expRCompYIsOneExt_uid42_fpInverseTest_b));
+ expRCompYIsOneExt_uid42_fpInverseTest_q <= expRCompYIsOneExt_uid42_fpInverseTest_o(5 downto 0);
+
+ -- expRCompYIsOne_uid43_fpInverseTest(BITSELECT,42)@2
+ expRCompYIsOne_uid43_fpInverseTest_in <= expRCompYIsOneExt_uid42_fpInverseTest_q(4 downto 0);
+ expRCompYIsOne_uid43_fpInverseTest_b <= expRCompYIsOne_uid43_fpInverseTest_in(4 downto 0);
+
+ -- cst2BiasM1_uid13_fpInverseTest(CONSTANT,12)
+ cst2BiasM1_uid13_fpInverseTest_q <= "11101";
+
+ -- expRCompExt_uid39_fpInverseTest(SUB,38)@2
+ expRCompExt_uid39_fpInverseTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid13_fpInverseTest_q);
+ expRCompExt_uid39_fpInverseTest_b <= STD_LOGIC_VECTOR("0" & redist7_expX_uid6_fpInverseTest_b_2_q);
+ expRCompExt_uid39_fpInverseTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid39_fpInverseTest_a) - UNSIGNED(expRCompExt_uid39_fpInverseTest_b));
+ expRCompExt_uid39_fpInverseTest_q <= expRCompExt_uid39_fpInverseTest_o(5 downto 0);
+
+ -- expRComp_uid40_fpInverseTest(BITSELECT,39)@2
+ expRComp_uid40_fpInverseTest_in <= expRCompExt_uid39_fpInverseTest_q(4 downto 0);
+ expRComp_uid40_fpInverseTest_b <= expRComp_uid40_fpInverseTest_in(4 downto 0);
+
+ -- GND(CONSTANT,0)
+ GND_q <= "0";
+
+ -- updatedY_uid32_fpInverseTest(BITJOIN,31)@0
+ updatedY_uid32_fpInverseTest_q <= GND_q & cstAllZWF_uid10_fpInverseTest_q;
+
+ -- fracXIsZero_uid31_fpInverseTest(LOGICAL,32)@0 + 1
+ fracXIsZero_uid31_fpInverseTest_a <= STD_LOGIC_VECTOR("0" & fracX_uid7_fpInverseTest_b);
+ fracXIsZero_uid31_fpInverseTest_qi <= "1" WHEN fracXIsZero_uid31_fpInverseTest_a = updatedY_uid32_fpInverseTest_q ELSE "0";
+ fracXIsZero_uid31_fpInverseTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsZero_uid31_fpInverseTest_qi, xout => fracXIsZero_uid31_fpInverseTest_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- redist2_fracXIsZero_uid31_fpInverseTest_q_2(DELAY,81)
+ redist2_fracXIsZero_uid31_fpInverseTest_q_2 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsZero_uid31_fpInverseTest_q, xout => redist2_fracXIsZero_uid31_fpInverseTest_q_2_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- expRCalc_uid48_fpInverseTest(MUX,47)@2 + 1
+ expRCalc_uid48_fpInverseTest_s <= redist2_fracXIsZero_uid31_fpInverseTest_q_2_q;
+ expRCalc_uid48_fpInverseTest_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ expRCalc_uid48_fpInverseTest_q <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (en = "1") THEN
+ CASE (expRCalc_uid48_fpInverseTest_s) IS
+ WHEN "0" => expRCalc_uid48_fpInverseTest_q <= expRComp_uid40_fpInverseTest_b;
+ WHEN "1" => expRCalc_uid48_fpInverseTest_q <= expRCompYIsOne_uid43_fpInverseTest_b;
+ WHEN OTHERS => expRCalc_uid48_fpInverseTest_q <= (others => '0');
+ END CASE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ -- cstAllZWE_uid12_fpInverseTest(CONSTANT,11)
+ cstAllZWE_uid12_fpInverseTest_q <= "00000";
+
+ -- excZ_x_uid21_fpInverseTest(LOGICAL,20)@2
+ excZ_x_uid21_fpInverseTest_q <= "1" WHEN redist7_expX_uid6_fpInverseTest_b_2_q = cstAllZWE_uid12_fpInverseTest_q ELSE "0";
+
+ -- redist5_excZ_x_uid21_fpInverseTest_q_1(DELAY,84)
+ redist5_excZ_x_uid21_fpInverseTest_q_1 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excZ_x_uid21_fpInverseTest_q, xout => redist5_excZ_x_uid21_fpInverseTest_q_1_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- udf_uid41_fpInverseTest(BITSELECT,40)@2
+ udf_uid41_fpInverseTest_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((6 downto 6 => expRCompExt_uid39_fpInverseTest_q(5)) & expRCompExt_uid39_fpInverseTest_q));
+ udf_uid41_fpInverseTest_b <= STD_LOGIC_VECTOR(udf_uid41_fpInverseTest_in(6 downto 6));
+
+ -- invExpXIsMax_uid27_fpInverseTest(LOGICAL,26)@2
+ invExpXIsMax_uid27_fpInverseTest_q <= not (expXIsMax_uid22_fpInverseTest_q);
+
+ -- InvExpXIsZero_uid28_fpInverseTest(LOGICAL,27)@2
+ InvExpXIsZero_uid28_fpInverseTest_q <= not (excZ_x_uid21_fpInverseTest_q);
+
+ -- excR_x_uid29_fpInverseTest(LOGICAL,28)@2
+ excR_x_uid29_fpInverseTest_q <= InvExpXIsZero_uid28_fpInverseTest_q and invExpXIsMax_uid27_fpInverseTest_q;
+
+ -- xRegAndUdf_uid49_fpInverseTest(LOGICAL,48)@2 + 1
+ xRegAndUdf_uid49_fpInverseTest_qi <= excR_x_uid29_fpInverseTest_q and udf_uid41_fpInverseTest_b;
+ xRegAndUdf_uid49_fpInverseTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => xRegAndUdf_uid49_fpInverseTest_qi, xout => xRegAndUdf_uid49_fpInverseTest_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- excI_x_uid25_fpInverseTest(LOGICAL,24)@2 + 1
+ excI_x_uid25_fpInverseTest_qi <= expXIsMax_uid22_fpInverseTest_q and redist4_fracXIsZero_uid23_fpInverseTest_q_2_q;
+ excI_x_uid25_fpInverseTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excI_x_uid25_fpInverseTest_qi, xout => excI_x_uid25_fpInverseTest_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- xIOrXRUdf_uid50_fpInverseTest(LOGICAL,49)@3
+ xIOrXRUdf_uid50_fpInverseTest_q <= excI_x_uid25_fpInverseTest_q or xRegAndUdf_uid49_fpInverseTest_q;
+
+ -- excSelBits_uid51_fpInverseTest(BITJOIN,50)@3
+ excSelBits_uid51_fpInverseTest_q <= excN_x_uid26_fpInverseTest_q & redist5_excZ_x_uid21_fpInverseTest_q_1_q & xIOrXRUdf_uid50_fpInverseTest_q;
+
+ -- outMuxSelEnc_uid52_fpInverseTest(LOOKUP,51)@3
+ outMuxSelEnc_uid52_fpInverseTest_combproc: PROCESS (excSelBits_uid51_fpInverseTest_q)
+ BEGIN
+ -- Begin reserved scope level
+ CASE (excSelBits_uid51_fpInverseTest_q) IS
+ WHEN "000" => outMuxSelEnc_uid52_fpInverseTest_q <= "01";
+ WHEN "001" => outMuxSelEnc_uid52_fpInverseTest_q <= "00";
+ WHEN "010" => outMuxSelEnc_uid52_fpInverseTest_q <= "10";
+ WHEN "011" => outMuxSelEnc_uid52_fpInverseTest_q <= "01";
+ WHEN "100" => outMuxSelEnc_uid52_fpInverseTest_q <= "11";
+ WHEN "101" => outMuxSelEnc_uid52_fpInverseTest_q <= "01";
+ WHEN "110" => outMuxSelEnc_uid52_fpInverseTest_q <= "01";
+ WHEN "111" => outMuxSelEnc_uid52_fpInverseTest_q <= "01";
+ WHEN OTHERS => -- unreachable
+ outMuxSelEnc_uid52_fpInverseTest_q <= (others => '-');
+ END CASE;
+ -- End reserved scope level
+ END PROCESS;
+
+ -- expRPostExc_uid55_fpInverseTest(MUX,54)@3
+ expRPostExc_uid55_fpInverseTest_s <= outMuxSelEnc_uid52_fpInverseTest_q;
+ expRPostExc_uid55_fpInverseTest_combproc: PROCESS (expRPostExc_uid55_fpInverseTest_s, en, cstAllZWE_uid12_fpInverseTest_q, expRCalc_uid48_fpInverseTest_q, cstAllOWE_uid9_fpInverseTest_q)
+ BEGIN
+ CASE (expRPostExc_uid55_fpInverseTest_s) IS
+ WHEN "00" => expRPostExc_uid55_fpInverseTest_q <= cstAllZWE_uid12_fpInverseTest_q;
+ WHEN "01" => expRPostExc_uid55_fpInverseTest_q <= expRCalc_uid48_fpInverseTest_q;
+ WHEN "10" => expRPostExc_uid55_fpInverseTest_q <= cstAllOWE_uid9_fpInverseTest_q;
+ WHEN "11" => expRPostExc_uid55_fpInverseTest_q <= cstAllOWE_uid9_fpInverseTest_q;
+ WHEN OTHERS => expRPostExc_uid55_fpInverseTest_q <= (others => '0');
+ END CASE;
+ END PROCESS;
+
+ -- cstNaNWF_uid11_fpInverseTest(CONSTANT,10)
+ cstNaNWF_uid11_fpInverseTest_q <= "0000000001";
+
+ -- memoryC1_uid64_inverseTables(LOOKUP,63)@0
+ memoryC1_uid64_inverseTables_combproc: PROCESS (yAddr_uid36_fpInverseTest_merged_bit_select_b)
+ BEGIN
+ -- Begin reserved scope level
+ CASE (yAddr_uid36_fpInverseTest_merged_bit_select_b) IS
+ WHEN "000000" => memoryC1_uid64_inverseTables_q <= "100000011";
+ WHEN "000001" => memoryC1_uid64_inverseTables_q <= "100001100";
+ WHEN "000010" => memoryC1_uid64_inverseTables_q <= "100010011";
+ WHEN "000011" => memoryC1_uid64_inverseTables_q <= "100011010";
+ WHEN "000100" => memoryC1_uid64_inverseTables_q <= "100100000";
+ WHEN "000101" => memoryC1_uid64_inverseTables_q <= "100100111";
+ WHEN "000110" => memoryC1_uid64_inverseTables_q <= "100101101";
+ WHEN "000111" => memoryC1_uid64_inverseTables_q <= "100110011";
+ WHEN "001000" => memoryC1_uid64_inverseTables_q <= "100111001";
+ WHEN "001001" => memoryC1_uid64_inverseTables_q <= "100111110";
+ WHEN "001010" => memoryC1_uid64_inverseTables_q <= "101000011";
+ WHEN "001011" => memoryC1_uid64_inverseTables_q <= "101001000";
+ WHEN "001100" => memoryC1_uid64_inverseTables_q <= "101001100";
+ WHEN "001101" => memoryC1_uid64_inverseTables_q <= "101010001";
+ WHEN "001110" => memoryC1_uid64_inverseTables_q <= "101010110";
+ WHEN "001111" => memoryC1_uid64_inverseTables_q <= "101011010";
+ WHEN "010000" => memoryC1_uid64_inverseTables_q <= "101011110";
+ WHEN "010001" => memoryC1_uid64_inverseTables_q <= "101100010";
+ WHEN "010010" => memoryC1_uid64_inverseTables_q <= "101100110";
+ WHEN "010011" => memoryC1_uid64_inverseTables_q <= "101101010";
+ WHEN "010100" => memoryC1_uid64_inverseTables_q <= "101101101";
+ WHEN "010101" => memoryC1_uid64_inverseTables_q <= "101110001";
+ WHEN "010110" => memoryC1_uid64_inverseTables_q <= "101110011";
+ WHEN "010111" => memoryC1_uid64_inverseTables_q <= "101111000";
+ WHEN "011000" => memoryC1_uid64_inverseTables_q <= "101111011";
+ WHEN "011001" => memoryC1_uid64_inverseTables_q <= "101111101";
+ WHEN "011010" => memoryC1_uid64_inverseTables_q <= "110000000";
+ WHEN "011011" => memoryC1_uid64_inverseTables_q <= "110000010";
+ WHEN "011100" => memoryC1_uid64_inverseTables_q <= "110000110";
+ WHEN "011101" => memoryC1_uid64_inverseTables_q <= "110001000";
+ WHEN "011110" => memoryC1_uid64_inverseTables_q <= "110001010";
+ WHEN "011111" => memoryC1_uid64_inverseTables_q <= "110001110";
+ WHEN "100000" => memoryC1_uid64_inverseTables_q <= "110001111";
+ WHEN "100001" => memoryC1_uid64_inverseTables_q <= "110010010";
+ WHEN "100010" => memoryC1_uid64_inverseTables_q <= "110010011";
+ WHEN "100011" => memoryC1_uid64_inverseTables_q <= "110010101";
+ WHEN "100100" => memoryC1_uid64_inverseTables_q <= "110011000";
+ WHEN "100101" => memoryC1_uid64_inverseTables_q <= "110011010";
+ WHEN "100110" => memoryC1_uid64_inverseTables_q <= "110011100";
+ WHEN "100111" => memoryC1_uid64_inverseTables_q <= "110011110";
+ WHEN "101000" => memoryC1_uid64_inverseTables_q <= "110100000";
+ WHEN "101001" => memoryC1_uid64_inverseTables_q <= "110100010";
+ WHEN "101010" => memoryC1_uid64_inverseTables_q <= "110100100";
+ WHEN "101011" => memoryC1_uid64_inverseTables_q <= "110100101";
+ WHEN "101100" => memoryC1_uid64_inverseTables_q <= "110100111";
+ WHEN "101101" => memoryC1_uid64_inverseTables_q <= "110101000";
+ WHEN "101110" => memoryC1_uid64_inverseTables_q <= "110101011";
+ WHEN "101111" => memoryC1_uid64_inverseTables_q <= "110101011";
+ WHEN "110000" => memoryC1_uid64_inverseTables_q <= "110101101";
+ WHEN "110001" => memoryC1_uid64_inverseTables_q <= "110101111";
+ WHEN "110010" => memoryC1_uid64_inverseTables_q <= "110110000";
+ WHEN "110011" => memoryC1_uid64_inverseTables_q <= "110110001";
+ WHEN "110100" => memoryC1_uid64_inverseTables_q <= "110110011";
+ WHEN "110101" => memoryC1_uid64_inverseTables_q <= "110110100";
+ WHEN "110110" => memoryC1_uid64_inverseTables_q <= "110110110";
+ WHEN "110111" => memoryC1_uid64_inverseTables_q <= "110110111";
+ WHEN "111000" => memoryC1_uid64_inverseTables_q <= "110111000";
+ WHEN "111001" => memoryC1_uid64_inverseTables_q <= "110111001";
+ WHEN "111010" => memoryC1_uid64_inverseTables_q <= "110111010";
+ WHEN "111011" => memoryC1_uid64_inverseTables_q <= "110111011";
+ WHEN "111100" => memoryC1_uid64_inverseTables_q <= "110111101";
+ WHEN "111101" => memoryC1_uid64_inverseTables_q <= "110111101";
+ WHEN "111110" => memoryC1_uid64_inverseTables_q <= "110111110";
+ WHEN "111111" => memoryC1_uid64_inverseTables_q <= "111000000";
+ WHEN OTHERS => -- unreachable
+ memoryC1_uid64_inverseTables_q <= (others => '-');
+ END CASE;
+ -- End reserved scope level
+ END PROCESS;
+
+ -- VCC(CONSTANT,1)
+ VCC_q <= "1";
+
+ -- oFracX_uid30_fpInverseTest(BITJOIN,29)@0
+ oFracX_uid30_fpInverseTest_q <= VCC_q & fracX_uid7_fpInverseTest_b;
+
+ -- y_uid34_fpInverseTest(BITSELECT,33)@0
+ y_uid34_fpInverseTest_in <= oFracX_uid30_fpInverseTest_q(9 downto 0);
+ y_uid34_fpInverseTest_b <= y_uid34_fpInverseTest_in(9 downto 0);
+
+ -- yAddr_uid36_fpInverseTest_merged_bit_select(BITSELECT,78)@0
+ yAddr_uid36_fpInverseTest_merged_bit_select_b <= y_uid34_fpInverseTest_b(9 downto 4);
+ yAddr_uid36_fpInverseTest_merged_bit_select_c <= y_uid34_fpInverseTest_b(3 downto 0);
+
+ -- prodXY_uid76_pT1_uid70_invPolyEval(MULT,75)@0 + 2
+ prodXY_uid76_pT1_uid70_invPolyEval_pr <= SIGNED(signed(resize(UNSIGNED(prodXY_uid76_pT1_uid70_invPolyEval_a0),5)) * SIGNED(prodXY_uid76_pT1_uid70_invPolyEval_b0));
+ prodXY_uid76_pT1_uid70_invPolyEval_component: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ prodXY_uid76_pT1_uid70_invPolyEval_a0 <= (others => '0');
+ prodXY_uid76_pT1_uid70_invPolyEval_b0 <= (others => '0');
+ prodXY_uid76_pT1_uid70_invPolyEval_s1 <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (en = "1") THEN
+ prodXY_uid76_pT1_uid70_invPolyEval_a0 <= yAddr_uid36_fpInverseTest_merged_bit_select_c;
+ prodXY_uid76_pT1_uid70_invPolyEval_b0 <= STD_LOGIC_VECTOR(memoryC1_uid64_inverseTables_q);
+ prodXY_uid76_pT1_uid70_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid76_pT1_uid70_invPolyEval_pr,13));
+ END IF;
+ END IF;
+ END PROCESS;
+ prodXY_uid76_pT1_uid70_invPolyEval_q <= prodXY_uid76_pT1_uid70_invPolyEval_s1;
+
+ -- osig_uid77_pT1_uid70_invPolyEval(BITSELECT,76)@2
+ osig_uid77_pT1_uid70_invPolyEval_b <= STD_LOGIC_VECTOR(prodXY_uid76_pT1_uid70_invPolyEval_q(12 downto 2));
+
+ -- highBBits_uid72_invPolyEval(BITSELECT,71)@2
+ highBBits_uid72_invPolyEval_b <= STD_LOGIC_VECTOR(osig_uid77_pT1_uid70_invPolyEval_b(10 downto 2));
+
+ -- redist0_yAddr_uid36_fpInverseTest_merged_bit_select_b_1(DELAY,79)
+ redist0_yAddr_uid36_fpInverseTest_merged_bit_select_b_1 : dspba_delay
+ GENERIC MAP ( width => 6, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => yAddr_uid36_fpInverseTest_merged_bit_select_b, xout => redist0_yAddr_uid36_fpInverseTest_merged_bit_select_b_1_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- memoryC0_uid61_inverseTables(LOOKUP,60)@1 + 1
+ memoryC0_uid61_inverseTables_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ memoryC0_uid61_inverseTables_q <= "010000";
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (en = "1") THEN
+ CASE (redist0_yAddr_uid36_fpInverseTest_merged_bit_select_b_1_q) IS
+ WHEN "000000" => memoryC0_uid61_inverseTables_q <= "010000";
+ WHEN "000001" => memoryC0_uid61_inverseTables_q <= "001111";
+ WHEN "000010" => memoryC0_uid61_inverseTables_q <= "001111";
+ WHEN "000011" => memoryC0_uid61_inverseTables_q <= "001111";
+ WHEN "000100" => memoryC0_uid61_inverseTables_q <= "001111";
+ WHEN "000101" => memoryC0_uid61_inverseTables_q <= "001110";
+ WHEN "000110" => memoryC0_uid61_inverseTables_q <= "001110";
+ WHEN "000111" => memoryC0_uid61_inverseTables_q <= "001110";
+ WHEN "001000" => memoryC0_uid61_inverseTables_q <= "001110";
+ WHEN "001001" => memoryC0_uid61_inverseTables_q <= "001110";
+ WHEN "001010" => memoryC0_uid61_inverseTables_q <= "001101";
+ WHEN "001011" => memoryC0_uid61_inverseTables_q <= "001101";
+ WHEN "001100" => memoryC0_uid61_inverseTables_q <= "001101";
+ WHEN "001101" => memoryC0_uid61_inverseTables_q <= "001101";
+ WHEN "001110" => memoryC0_uid61_inverseTables_q <= "001101";
+ WHEN "001111" => memoryC0_uid61_inverseTables_q <= "001100";
+ WHEN "010000" => memoryC0_uid61_inverseTables_q <= "001100";
+ WHEN "010001" => memoryC0_uid61_inverseTables_q <= "001100";
+ WHEN "010010" => memoryC0_uid61_inverseTables_q <= "001100";
+ WHEN "010011" => memoryC0_uid61_inverseTables_q <= "001100";
+ WHEN "010100" => memoryC0_uid61_inverseTables_q <= "001100";
+ WHEN "010101" => memoryC0_uid61_inverseTables_q <= "001100";
+ WHEN "010110" => memoryC0_uid61_inverseTables_q <= "001011";
+ WHEN "010111" => memoryC0_uid61_inverseTables_q <= "001011";
+ WHEN "011000" => memoryC0_uid61_inverseTables_q <= "001011";
+ WHEN "011001" => memoryC0_uid61_inverseTables_q <= "001011";
+ WHEN "011010" => memoryC0_uid61_inverseTables_q <= "001011";
+ WHEN "011011" => memoryC0_uid61_inverseTables_q <= "001011";
+ WHEN "011100" => memoryC0_uid61_inverseTables_q <= "001011";
+ WHEN "011101" => memoryC0_uid61_inverseTables_q <= "001011";
+ WHEN "011110" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "011111" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "100000" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "100001" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "100010" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "100011" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "100100" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "100101" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "100110" => memoryC0_uid61_inverseTables_q <= "001010";
+ WHEN "100111" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "101000" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "101001" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "101010" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "101011" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "101100" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "101101" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "101110" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "101111" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "110000" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "110001" => memoryC0_uid61_inverseTables_q <= "001001";
+ WHEN "110010" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "110011" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "110100" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "110101" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "110110" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "110111" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "111000" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "111001" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "111010" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "111011" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "111100" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "111101" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "111110" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN "111111" => memoryC0_uid61_inverseTables_q <= "001000";
+ WHEN OTHERS => -- unreachable
+ memoryC0_uid61_inverseTables_q <= (others => '-');
+ END CASE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ -- memoryC0_uid60_inverseTables(LOOKUP,59)@1 + 1
+ memoryC0_uid60_inverseTables_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ memoryC0_uid60_inverseTables_q <= "0000000100";
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (en = "1") THEN
+ CASE (redist0_yAddr_uid36_fpInverseTest_merged_bit_select_b_1_q) IS
+ WHEN "000000" => memoryC0_uid60_inverseTables_q <= "0000000100";
+ WHEN "000001" => memoryC0_uid60_inverseTables_q <= "1100000111";
+ WHEN "000010" => memoryC0_uid60_inverseTables_q <= "1000010011";
+ WHEN "000011" => memoryC0_uid60_inverseTables_q <= "0100100110";
+ WHEN "000100" => memoryC0_uid60_inverseTables_q <= "0001000000";
+ WHEN "000101" => memoryC0_uid60_inverseTables_q <= "1101100000";
+ WHEN "000110" => memoryC0_uid60_inverseTables_q <= "1010000111";
+ WHEN "000111" => memoryC0_uid60_inverseTables_q <= "0110110100";
+ WHEN "001000" => memoryC0_uid60_inverseTables_q <= "0011100111";
+ WHEN "001001" => memoryC0_uid60_inverseTables_q <= "0000100000";
+ WHEN "001010" => memoryC0_uid60_inverseTables_q <= "1101011110";
+ WHEN "001011" => memoryC0_uid60_inverseTables_q <= "1010100001";
+ WHEN "001100" => memoryC0_uid60_inverseTables_q <= "0111101001";
+ WHEN "001101" => memoryC0_uid60_inverseTables_q <= "0100110110";
+ WHEN "001110" => memoryC0_uid60_inverseTables_q <= "0010000111";
+ WHEN "001111" => memoryC0_uid60_inverseTables_q <= "1111011101";
+ WHEN "010000" => memoryC0_uid60_inverseTables_q <= "1100110111";
+ WHEN "010001" => memoryC0_uid60_inverseTables_q <= "1010010101";
+ WHEN "010010" => memoryC0_uid60_inverseTables_q <= "0111110111";
+ WHEN "010011" => memoryC0_uid60_inverseTables_q <= "0101011101";
+ WHEN "010100" => memoryC0_uid60_inverseTables_q <= "0011000111";
+ WHEN "010101" => memoryC0_uid60_inverseTables_q <= "0000110100";
+ WHEN "010110" => memoryC0_uid60_inverseTables_q <= "1110100101";
+ WHEN "010111" => memoryC0_uid60_inverseTables_q <= "1100011000";
+ WHEN "011000" => memoryC0_uid60_inverseTables_q <= "1010001111";
+ WHEN "011001" => memoryC0_uid60_inverseTables_q <= "1000001010";
+ WHEN "011010" => memoryC0_uid60_inverseTables_q <= "0110000111";
+ WHEN "011011" => memoryC0_uid60_inverseTables_q <= "0100000111";
+ WHEN "011100" => memoryC0_uid60_inverseTables_q <= "0010001001";
+ WHEN "011101" => memoryC0_uid60_inverseTables_q <= "0000001111";
+ WHEN "011110" => memoryC0_uid60_inverseTables_q <= "1110010111";
+ WHEN "011111" => memoryC0_uid60_inverseTables_q <= "1100100001";
+ WHEN "100000" => memoryC0_uid60_inverseTables_q <= "1010101111";
+ WHEN "100001" => memoryC0_uid60_inverseTables_q <= "1000111110";
+ WHEN "100010" => memoryC0_uid60_inverseTables_q <= "0111010000";
+ WHEN "100011" => memoryC0_uid60_inverseTables_q <= "0101100100";
+ WHEN "100100" => memoryC0_uid60_inverseTables_q <= "0011111010";
+ WHEN "100101" => memoryC0_uid60_inverseTables_q <= "0010010010";
+ WHEN "100110" => memoryC0_uid60_inverseTables_q <= "0000101100";
+ WHEN "100111" => memoryC0_uid60_inverseTables_q <= "1111001000";
+ WHEN "101000" => memoryC0_uid60_inverseTables_q <= "1101100110";
+ WHEN "101001" => memoryC0_uid60_inverseTables_q <= "1100000110";
+ WHEN "101010" => memoryC0_uid60_inverseTables_q <= "1010101000";
+ WHEN "101011" => memoryC0_uid60_inverseTables_q <= "1001001100";
+ WHEN "101100" => memoryC0_uid60_inverseTables_q <= "0111110001";
+ WHEN "101101" => memoryC0_uid60_inverseTables_q <= "0110011000";
+ WHEN "101110" => memoryC0_uid60_inverseTables_q <= "0101000000";
+ WHEN "101111" => memoryC0_uid60_inverseTables_q <= "0011101011";
+ WHEN "110000" => memoryC0_uid60_inverseTables_q <= "0010010110";
+ WHEN "110001" => memoryC0_uid60_inverseTables_q <= "0001000011";
+ WHEN "110010" => memoryC0_uid60_inverseTables_q <= "1111110010";
+ WHEN "110011" => memoryC0_uid60_inverseTables_q <= "1110100010";
+ WHEN "110100" => memoryC0_uid60_inverseTables_q <= "1101010011";
+ WHEN "110101" => memoryC0_uid60_inverseTables_q <= "1100000110";
+ WHEN "110110" => memoryC0_uid60_inverseTables_q <= "1010111010";
+ WHEN "110111" => memoryC0_uid60_inverseTables_q <= "1001101111";
+ WHEN "111000" => memoryC0_uid60_inverseTables_q <= "1000100110";
+ WHEN "111001" => memoryC0_uid60_inverseTables_q <= "0111011110";
+ WHEN "111010" => memoryC0_uid60_inverseTables_q <= "0110010111";
+ WHEN "111011" => memoryC0_uid60_inverseTables_q <= "0101010001";
+ WHEN "111100" => memoryC0_uid60_inverseTables_q <= "0100001100";
+ WHEN "111101" => memoryC0_uid60_inverseTables_q <= "0011001001";
+ WHEN "111110" => memoryC0_uid60_inverseTables_q <= "0010000110";
+ WHEN "111111" => memoryC0_uid60_inverseTables_q <= "0001000100";
+ WHEN OTHERS => -- unreachable
+ memoryC0_uid60_inverseTables_q <= (others => '-');
+ END CASE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ -- os_uid62_inverseTables(BITJOIN,61)@2
+ os_uid62_inverseTables_q <= memoryC0_uid61_inverseTables_q & memoryC0_uid60_inverseTables_q;
+
+ -- s1sumAHighB_uid73_invPolyEval(ADD,72)@2
+ s1sumAHighB_uid73_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((16 downto 16 => os_uid62_inverseTables_q(15)) & os_uid62_inverseTables_q));
+ s1sumAHighB_uid73_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((16 downto 9 => highBBits_uid72_invPolyEval_b(8)) & highBBits_uid72_invPolyEval_b));
+ s1sumAHighB_uid73_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(s1sumAHighB_uid73_invPolyEval_a) + SIGNED(s1sumAHighB_uid73_invPolyEval_b));
+ s1sumAHighB_uid73_invPolyEval_q <= s1sumAHighB_uid73_invPolyEval_o(16 downto 0);
+
+ -- lowRangeB_uid71_invPolyEval(BITSELECT,70)@2
+ lowRangeB_uid71_invPolyEval_in <= osig_uid77_pT1_uid70_invPolyEval_b(1 downto 0);
+ lowRangeB_uid71_invPolyEval_b <= lowRangeB_uid71_invPolyEval_in(1 downto 0);
+
+ -- s1_uid74_invPolyEval(BITJOIN,73)@2
+ s1_uid74_invPolyEval_q <= s1sumAHighB_uid73_invPolyEval_q & lowRangeB_uid71_invPolyEval_b;
+
+ -- fxpInverseRes_uid44_fpInverseTest(BITSELECT,43)@2
+ fxpInverseRes_uid44_fpInverseTest_in <= s1_uid74_invPolyEval_q(15 downto 0);
+ fxpInverseRes_uid44_fpInverseTest_b <= fxpInverseRes_uid44_fpInverseTest_in(15 downto 5);
+
+ -- fxpInverseResFrac_uid46_fpInverseTest(BITSELECT,45)@2
+ fxpInverseResFrac_uid46_fpInverseTest_in <= fxpInverseRes_uid44_fpInverseTest_b(9 downto 0);
+ fxpInverseResFrac_uid46_fpInverseTest_b <= fxpInverseResFrac_uid46_fpInverseTest_in(9 downto 0);
+
+ -- redist1_fxpInverseResFrac_uid46_fpInverseTest_b_1(DELAY,80)
+ redist1_fxpInverseResFrac_uid46_fpInverseTest_b_1 : dspba_delay
+ GENERIC MAP ( width => 10, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fxpInverseResFrac_uid46_fpInverseTest_b, xout => redist1_fxpInverseResFrac_uid46_fpInverseTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- redist3_fracXIsZero_uid31_fpInverseTest_q_3(DELAY,82)
+ redist3_fracXIsZero_uid31_fpInverseTest_q_3 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => redist2_fracXIsZero_uid31_fpInverseTest_q_2_q, xout => redist3_fracXIsZero_uid31_fpInverseTest_q_3_q, ena => en(0), clk => clk, aclr => areset );
+
+ -- fracRCalc_uid47_fpInverseTest(MUX,46)@3
+ fracRCalc_uid47_fpInverseTest_s <= redist3_fracXIsZero_uid31_fpInverseTest_q_3_q;
+ fracRCalc_uid47_fpInverseTest_combproc: PROCESS (fracRCalc_uid47_fpInverseTest_s, en, redist1_fxpInverseResFrac_uid46_fpInverseTest_b_1_q, cstAllZWF_uid10_fpInverseTest_q)
+ BEGIN
+ CASE (fracRCalc_uid47_fpInverseTest_s) IS
+ WHEN "0" => fracRCalc_uid47_fpInverseTest_q <= redist1_fxpInverseResFrac_uid46_fpInverseTest_b_1_q;
+ WHEN "1" => fracRCalc_uid47_fpInverseTest_q <= cstAllZWF_uid10_fpInverseTest_q;
+ WHEN OTHERS => fracRCalc_uid47_fpInverseTest_q <= (others => '0');
+ END CASE;
+ END PROCESS;
+
+ -- fracRPostExc_uid54_fpInverseTest(MUX,53)@3
+ fracRPostExc_uid54_fpInverseTest_s <= outMuxSelEnc_uid52_fpInverseTest_q;
+ fracRPostExc_uid54_fpInverseTest_combproc: PROCESS (fracRPostExc_uid54_fpInverseTest_s, en, cstAllZWF_uid10_fpInverseTest_q, fracRCalc_uid47_fpInverseTest_q, cstNaNWF_uid11_fpInverseTest_q)
+ BEGIN
+ CASE (fracRPostExc_uid54_fpInverseTest_s) IS
+ WHEN "00" => fracRPostExc_uid54_fpInverseTest_q <= cstAllZWF_uid10_fpInverseTest_q;
+ WHEN "01" => fracRPostExc_uid54_fpInverseTest_q <= fracRCalc_uid47_fpInverseTest_q;
+ WHEN "10" => fracRPostExc_uid54_fpInverseTest_q <= cstAllZWF_uid10_fpInverseTest_q;
+ WHEN "11" => fracRPostExc_uid54_fpInverseTest_q <= cstNaNWF_uid11_fpInverseTest_q;
+ WHEN OTHERS => fracRPostExc_uid54_fpInverseTest_q <= (others => '0');
+ END CASE;
+ END PROCESS;
+
+ -- R_uid58_fpInverseTest(BITJOIN,57)@3
+ R_uid58_fpInverseTest_q <= signR_uid57_fpInverseTest_q & expRPostExc_uid55_fpInverseTest_q & fracRPostExc_uid54_fpInverseTest_q;
+
+ -- xOut(GPOUT,4)@3
+ q <= R_uid58_fpInverseTest_q;
+
+END normal;
diff --git a/ip/ip_fp_inv_sim.f b/ip/ip_fp_inv_sim.f
new file mode 100644
index 0000000..ea0272e
--- /dev/null
+++ b/ip/ip_fp_inv_sim.f
@@ -0,0 +1 @@
+ip_fp_inv_sim/ip_fp_inv.vo
diff --git a/ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl b/ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl
new file mode 100644
index 0000000..58382a2
--- /dev/null
+++ b/ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl
@@ -0,0 +1,278 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2023.10.31.13:44:11
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_inv
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_inv is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_fp_inv"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] {
+ set QUARTUS_INSTALL_DIR "/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
+ set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
+ set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
+ set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] {
+ set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+ set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+ scripterconf -tcl
+ createdesign "$TOP_LEVEL_NAME" "."
+ opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+ echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries
+ensure_lib ./libraries/work
+vmap work ./libraries/work
+ensure_lib ./libraries/altera_ver
+vmap altera_ver ./libraries/altera_ver
+ensure_lib ./libraries/lpm_ver
+vmap lpm_ver ./libraries/lpm_ver
+ensure_lib ./libraries/sgate_ver
+vmap sgate_ver ./libraries/sgate_ver
+ensure_lib ./libraries/altera_mf_ver
+vmap altera_mf_ver ./libraries/altera_mf_ver
+ensure_lib ./libraries/altera_lnsim_ver
+vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
+ensure_lib ./libraries/cyclonev_ver
+vmap cyclonev_ver ./libraries/cyclonev_ver
+ensure_lib ./libraries/cyclonev_hssi_ver
+vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
+ensure_lib ./libraries/cyclonev_pcie_hip_ver
+vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_inv.vo"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "file_copy -- Copy ROM/RAM files to simulation directory"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo " For most designs, this should be overridden"
+ echo " to enable the elab/elab_debug aliases."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
+ echo
+ echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
+ echo
+ echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
+ echo
+ echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
diff --git a/ip/ip_fp_inv_sim/cadence/cds.lib b/ip/ip_fp_inv_sim/cadence/cds.lib
new file mode 100644
index 0000000..b2eae0a
--- /dev/null
+++ b/ip/ip_fp_inv_sim/cadence/cds.lib
@@ -0,0 +1,19 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./libraries/work/
+DEFINE altera_ver ./libraries/altera_ver/
+DEFINE lpm_ver ./libraries/lpm_ver/
+DEFINE sgate_ver ./libraries/sgate_ver/
+DEFINE altera_mf_ver ./libraries/altera_mf_ver/
+DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/
+DEFINE cyclonev_ver ./libraries/cyclonev_ver/
+DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
+DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
diff --git a/ip/ip_fp_inv_sim/cadence/hdl.var b/ip/ip_fp_inv_sim/cadence/hdl.var
new file mode 100644
index 0000000..c1b7814
--- /dev/null
+++ b/ip/ip_fp_inv_sim/cadence/hdl.var
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
diff --git a/ip/ip_fp_inv_sim/cadence/ncsim_setup.sh b/ip/ip_fp_inv_sim/cadence/ncsim_setup.sh
new file mode 100755
index 0000000..ccdef9e
--- /dev/null
+++ b/ip/ip_fp_inv_sim/cadence/ncsim_setup.sh
@@ -0,0 +1,195 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2023.10.31.13:44:11
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_inv
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_inv is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2023.10.31.13:44:11
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_fp_inv"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_inv.vo"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ export GENERIC_PARAM_COMPAT_CHECK=1
+ ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi
diff --git a/ip/ip_fp_inv_sim/ip_fp_inv.vo b/ip/ip_fp_inv_sim/ip_fp_inv.vo
new file mode 100644
index 0000000..212c7fa
--- /dev/null
+++ b/ip/ip_fp_inv_sim/ip_fp_inv.vo
@@ -0,0 +1,862 @@
+//IP Functional Simulation Model
+//VERSION_BEGIN 20.1 cbx_mgl 2020:11:11:17:50:46:SJ cbx_simgen 2020:11:11:17:03:37:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2020 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions
+// and other software and tools, and any partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors. Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// You may only use these simulation model output files for simulation
+// purposes and expressly not for synthesis or any other purposes (in which
+// event Intel disclaims all warranties of any kind).
+
+
+//synopsys translate_off
+
+//synthesis_resources = lut 80 mux21 15 oper_add 3 oper_mult 1 oper_mux 40
+`timescale 1 ps / 1 ps
+module ip_fp_inv
+ (
+ a,
+ areset,
+ clk,
+ en,
+ q) /* synthesis synthesis_clearbox=1 */;
+ input [15:0] a;
+ input areset;
+ input clk;
+ input [0:0] en;
+ output [15:0] q;
+
+ reg n00l;
+ reg n00O;
+ reg n0i;
+ reg n0ii;
+ reg n0il;
+ reg n0iO;
+ reg n0li;
+ reg n0ll;
+ reg n0lO;
+ reg n0O;
+ reg n0Oi;
+ reg n0Ol;
+ reg n0OO;
+ reg n1iO;
+ reg n1l;
+ reg n1li;
+ reg n1ll;
+ reg n1O;
+ reg n1Ol;
+ reg ni0i;
+ reg ni0l;
+ reg ni0O;
+ reg ni1i;
+ reg ni1l;
+ reg ni1O;
+ reg niii;
+ reg niil;
+ reg niili;
+ reg niill;
+ reg niilO;
+ reg niiO;
+ reg niiOi;
+ reg niiOl;
+ reg niiOO;
+ reg nil0i;
+ reg nil0l;
+ reg nil0O;
+ reg nil1i;
+ reg nil1l;
+ reg nil1O;
+ reg nili;
+ reg nilii;
+ reg nilil;
+ reg niliO;
+ reg nill;
+ reg nilli;
+ reg nilll;
+ reg nillO;
+ reg nilOi;
+ reg nilOl;
+ reg nilOO;
+ reg niO0i;
+ reg niO0l;
+ reg niO0O;
+ reg niO1i;
+ reg niO1l;
+ reg niO1O;
+ reg niOii;
+ reg niOil;
+ reg niOiO;
+ reg niOli;
+ reg niOll;
+ reg niOlO;
+ reg niOOi;
+ reg niOOl;
+ reg niOOO;
+ reg nl11i;
+ reg nl11l;
+ reg nlO0i;
+ reg nlO0O;
+ reg nlO1l;
+ reg nlOii;
+ reg nlOil;
+ reg nlOiO;
+ reg nlOli;
+ reg nlOll;
+ reg nlOlO;
+ reg nlOOi;
+ wire wire_n0l_ENA;
+ reg n1Oi;
+ reg nlO0l;
+ wire wire_n1lO_ENA;
+ wire wire_nii_dataout;
+ wire wire_nil_dataout;
+ wire wire_niO_dataout;
+ wire wire_nli_dataout;
+ wire wire_nll_dataout;
+ wire wire_nllii_dataout;
+ wire wire_nllil_dataout;
+ wire wire_nlliO_dataout;
+ wire wire_nllli_dataout;
+ wire wire_nllll_dataout;
+ wire wire_nlllO_dataout;
+ wire wire_nllOi_dataout;
+ wire wire_nllOl_dataout;
+ wire wire_nllOO_dataout;
+ wire wire_nlO1i_dataout;
+ wire [6:0] wire_ni_o;
+ wire [6:0] wire_nlO_o;
+ wire [16:0] wire_nlO1O_o;
+ wire [13:0] wire_nilO_o;
+ wire wire_n00i_o;
+ wire wire_n01i_o;
+ wire wire_n01l_o;
+ wire wire_n01O_o;
+ wire wire_n10i_o;
+ wire wire_n10l_o;
+ wire wire_n10O_o;
+ wire wire_n11i_o;
+ wire wire_n11l_o;
+ wire wire_n11O_o;
+ wire wire_n1ii_o;
+ wire wire_n1il_o;
+ wire wire_n1OO_o;
+ wire wire_niOi_o;
+ wire wire_niOl_o;
+ wire wire_niOO_o;
+ wire wire_nl0i_o;
+ wire wire_nl0l_o;
+ wire wire_nl0O_o;
+ wire wire_nl1i_o;
+ wire wire_nl1l_o;
+ wire wire_nl1O_o;
+ wire wire_nlii_o;
+ wire wire_nlil_o;
+ wire wire_nlilO_o;
+ wire wire_nliO_o;
+ wire wire_nliOi_o;
+ wire wire_nliOl_o;
+ wire wire_nliOO_o;
+ wire wire_nll0i_o;
+ wire wire_nll0l_o;
+ wire wire_nll0O_o;
+ wire wire_nll1i_o;
+ wire wire_nll1l_o;
+ wire wire_nll1O_o;
+ wire wire_nlli_o;
+ wire wire_nlll_o;
+ wire wire_nllO_o;
+ wire wire_nlOOl_o;
+ wire wire_nlOOO_o;
+ wire nii0i;
+ wire nii0l;
+ wire nii0O;
+ wire nii1l;
+ wire nii1O;
+ wire niiii;
+
+ initial
+ begin
+ n00l = 0;
+ n00O = 0;
+ n0i = 0;
+ n0ii = 0;
+ n0il = 0;
+ n0iO = 0;
+ n0li = 0;
+ n0ll = 0;
+ n0lO = 0;
+ n0O = 0;
+ n0Oi = 0;
+ n0Ol = 0;
+ n0OO = 0;
+ n1iO = 0;
+ n1l = 0;
+ n1li = 0;
+ n1ll = 0;
+ n1O = 0;
+ n1Ol = 0;
+ ni0i = 0;
+ ni0l = 0;
+ ni0O = 0;
+ ni1i = 0;
+ ni1l = 0;
+ ni1O = 0;
+ niii = 0;
+ niil = 0;
+ niili = 0;
+ niill = 0;
+ niilO = 0;
+ niiO = 0;
+ niiOi = 0;
+ niiOl = 0;
+ niiOO = 0;
+ nil0i = 0;
+ nil0l = 0;
+ nil0O = 0;
+ nil1i = 0;
+ nil1l = 0;
+ nil1O = 0;
+ nili = 0;
+ nilii = 0;
+ nilil = 0;
+ niliO = 0;
+ nill = 0;
+ nilli = 0;
+ nilll = 0;
+ nillO = 0;
+ nilOi = 0;
+ nilOl = 0;
+ nilOO = 0;
+ niO0i = 0;
+ niO0l = 0;
+ niO0O = 0;
+ niO1i = 0;
+ niO1l = 0;
+ niO1O = 0;
+ niOii = 0;
+ niOil = 0;
+ niOiO = 0;
+ niOli = 0;
+ niOll = 0;
+ niOlO = 0;
+ niOOi = 0;
+ niOOl = 0;
+ niOOO = 0;
+ nl11i = 0;
+ nl11l = 0;
+ nlO0i = 0;
+ nlO0O = 0;
+ nlO1l = 0;
+ nlOii = 0;
+ nlOil = 0;
+ nlOiO = 0;
+ nlOli = 0;
+ nlOll = 0;
+ nlOlO = 0;
+ nlOOi = 0;
+ end
+ always @ ( posedge clk or posedge areset)
+ begin
+ if (areset == 1'b1)
+ begin
+ n00l <= 0;
+ n00O <= 0;
+ n0i <= 0;
+ n0ii <= 0;
+ n0il <= 0;
+ n0iO <= 0;
+ n0li <= 0;
+ n0ll <= 0;
+ n0lO <= 0;
+ n0O <= 0;
+ n0Oi <= 0;
+ n0Ol <= 0;
+ n0OO <= 0;
+ n1iO <= 0;
+ n1l <= 0;
+ n1li <= 0;
+ n1ll <= 0;
+ n1O <= 0;
+ n1Ol <= 0;
+ ni0i <= 0;
+ ni0l <= 0;
+ ni0O <= 0;
+ ni1i <= 0;
+ ni1l <= 0;
+ ni1O <= 0;
+ niii <= 0;
+ niil <= 0;
+ niili <= 0;
+ niill <= 0;
+ niilO <= 0;
+ niiO <= 0;
+ niiOi <= 0;
+ niiOl <= 0;
+ niiOO <= 0;
+ nil0i <= 0;
+ nil0l <= 0;
+ nil0O <= 0;
+ nil1i <= 0;
+ nil1l <= 0;
+ nil1O <= 0;
+ nili <= 0;
+ nilii <= 0;
+ nilil <= 0;
+ niliO <= 0;
+ nill <= 0;
+ nilli <= 0;
+ nilll <= 0;
+ nillO <= 0;
+ nilOi <= 0;
+ nilOl <= 0;
+ nilOO <= 0;
+ niO0i <= 0;
+ niO0l <= 0;
+ niO0O <= 0;
+ niO1i <= 0;
+ niO1l <= 0;
+ niO1O <= 0;
+ niOii <= 0;
+ niOil <= 0;
+ niOiO <= 0;
+ niOli <= 0;
+ niOll <= 0;
+ niOlO <= 0;
+ niOOi <= 0;
+ niOOl <= 0;
+ niOOO <= 0;
+ nl11i <= 0;
+ nl11l <= 0;
+ nlO0i <= 0;
+ nlO0O <= 0;
+ nlO1l <= 0;
+ nlOii <= 0;
+ nlOil <= 0;
+ nlOiO <= 0;
+ nlOli <= 0;
+ nlOll <= 0;
+ nlOlO <= 0;
+ nlOOi <= 0;
+ end
+ else if (wire_n0l_ENA == 1'b1)
+ begin
+ n00l <= wire_nilO_o[5];
+ n00O <= wire_nilO_o[6];
+ n0i <= wire_nli_dataout;
+ n0ii <= wire_nilO_o[7];
+ n0il <= wire_nilO_o[8];
+ n0iO <= wire_nilO_o[9];
+ n0li <= wire_nilO_o[10];
+ n0ll <= wire_nilO_o[11];
+ n0lO <= wire_nilO_o[13];
+ n0O <= wire_nll_dataout;
+ n0Oi <= wire_niOi_o;
+ n0Ol <= wire_niOl_o;
+ n0OO <= wire_niOO_o;
+ n1iO <= wire_n01i_o;
+ n1l <= wire_nil_dataout;
+ n1li <= wire_n01l_o;
+ n1ll <= wire_n01O_o;
+ n1O <= wire_niO_dataout;
+ n1Ol <= wire_nilO_o[4];
+ ni0i <= wire_nl0i_o;
+ ni0l <= wire_nl0l_o;
+ ni0O <= niiii;
+ ni1i <= wire_nl1i_o;
+ ni1l <= wire_nl1l_o;
+ ni1O <= wire_nl1O_o;
+ niii <= a[0];
+ niil <= a[1];
+ niili <= nii0l;
+ niill <= niili;
+ niilO <= nil1l;
+ niiO <= a[2];
+ niiOi <= nil1O;
+ niiOl <= nil0i;
+ niiOO <= nil0l;
+ nil0i <= a[12];
+ nil0l <= a[13];
+ nil0O <= a[14];
+ nil1i <= nil0O;
+ nil1l <= a[10];
+ nil1O <= a[11];
+ nili <= a[3];
+ nilii <= (nii0i & (~ niill));
+ nilil <= niliO;
+ niliO <= nilli;
+ nill <= wire_nii_dataout;
+ nilli <= a[15];
+ nilll <= nii1O;
+ nillO <= nilll;
+ nilOi <= nii1l;
+ nilOl <= (wire_nlO_o[6] & ((~ nii0i) & (~ nii1l)));
+ nilOO <= (nii0i & niill);
+ niO0i <= a[7];
+ niO0l <= a[8];
+ niO0O <= a[9];
+ niO1i <= a[4];
+ niO1l <= a[5];
+ niO1O <= a[6];
+ niOii <= wire_nlO1O_o[3];
+ niOil <= wire_nlO1O_o[4];
+ niOiO <= wire_nlO1O_o[5];
+ niOli <= wire_nlO1O_o[6];
+ niOll <= wire_nlO1O_o[7];
+ niOlO <= wire_nlO1O_o[8];
+ niOOi <= wire_nlO1O_o[9];
+ niOOl <= wire_nlO1O_o[10];
+ niOOO <= wire_nlO1O_o[11];
+ nl11i <= wire_nlO1O_o[12];
+ nl11l <= nillO;
+ nlO0i <= wire_nlOOO_o;
+ nlO0O <= wire_n11l_o;
+ nlO1l <= wire_nlOOl_o;
+ nlOii <= wire_n11O_o;
+ nlOil <= wire_n10i_o;
+ nlOiO <= wire_n10l_o;
+ nlOli <= wire_n10O_o;
+ nlOll <= wire_n1ii_o;
+ nlOlO <= wire_n1il_o;
+ nlOOi <= wire_n1OO_o;
+ end
+ end
+ assign
+ wire_n0l_ENA = en[0];
+ initial
+ begin
+ n1Oi = 0;
+ nlO0l = 0;
+ end
+ always @ ( posedge clk or posedge areset)
+ begin
+ if (areset == 1'b1)
+ begin
+ n1Oi <= 1;
+ nlO0l <= 1;
+ end
+ else if (wire_n1lO_ENA == 1'b1)
+ begin
+ n1Oi <= wire_n00i_o;
+ nlO0l <= wire_n11i_o;
+ end
+ end
+ assign
+ wire_n1lO_ENA = en[0];
+ event n1Oi_event;
+ event nlO0l_event;
+ initial
+ #1 ->n1Oi_event;
+ initial
+ #1 ->nlO0l_event;
+ always @(n1Oi_event)
+ n1Oi <= 1;
+ always @(nlO0l_event)
+ nlO0l <= 1;
+ assign wire_nii_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[1] : wire_ni_o[1];
+ assign wire_nil_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[2] : wire_ni_o[2];
+ assign wire_niO_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[3] : wire_ni_o[3];
+ assign wire_nli_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[4] : wire_ni_o[4];
+ assign wire_nll_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[5] : wire_ni_o[5];
+ and(wire_nllii_dataout, niOii, (~ nl11l));
+ and(wire_nllil_dataout, niOil, (~ nl11l));
+ and(wire_nlliO_dataout, niOiO, (~ nl11l));
+ and(wire_nllli_dataout, niOli, (~ nl11l));
+ and(wire_nllll_dataout, niOll, (~ nl11l));
+ and(wire_nlllO_dataout, niOlO, (~ nl11l));
+ and(wire_nllOi_dataout, niOOi, (~ nl11l));
+ and(wire_nllOl_dataout, niOOl, (~ nl11l));
+ and(wire_nllOO_dataout, niOOO, (~ nl11l));
+ and(wire_nlO1i_dataout, nl11i, (~ nl11l));
+ oper_add ni
+ (
+ .a({1'b1, (~ nil1i), (~ niiOO), (~ niiOl), (~ niiOi), (~ niilO), 1'b1}),
+ .b({1'b0, {4{1'b1}}, 1'b0, 1'b1}),
+ .cin(1'b0),
+ .cout(),
+ .o(wire_ni_o));
+ defparam
+ ni.sgate_representation = 0,
+ ni.width_a = 7,
+ ni.width_b = 7,
+ ni.width_o = 7;
+ oper_add nlO
+ (
+ .a({1'b1, (~ nil1i), (~ niiOO), (~ niiOl), (~ niiOi), (~ niilO), 1'b1}),
+ .b({1'b0, {3{1'b1}}, 1'b0, {2{1'b1}}}),
+ .cin(1'b0),
+ .cout(),
+ .o(wire_nlO_o));
+ defparam
+ nlO.sgate_representation = 0,
+ nlO.width_a = 7,
+ nlO.width_b = 7,
+ nlO.width_o = 7;
+ oper_add nlO1O
+ (
+ .a({{2{1'b0}}, n1Oi, n1ll, n1li, n1iO, nlOOi, nlOlO, nlOll, nlOli, nlOiO, nlOil, nlOii, nlO0O, nlO0l, nlO0i, nlO1l}),
+ .b({{9{n0lO}}, n0ll, n0li, n0iO, n0il, n0ii, n00O, n00l, n1Ol}),
+ .cin(1'b0),
+ .cout(),
+ .o(wire_nlO1O_o));
+ defparam
+ nlO1O.sgate_representation = 0,
+ nlO1O.width_a = 17,
+ nlO1O.width_b = 17,
+ nlO1O.width_o = 17;
+ oper_mult nilO
+ (
+ .a({1'b0, nili, niiO, niil, niii}),
+ .b({ni0O, ni0l, ni0i, ni1O, ni1l, ni1i, n0OO, n0Ol, n0Oi}),
+ .o(wire_nilO_o));
+ defparam
+ nilO.sgate_representation = 1,
+ nilO.width_a = 5,
+ nilO.width_b = 9,
+ nilO.width_o = 14;
+ oper_mux n00i
+ (
+ .data({{63{1'b0}}, 1'b1}),
+ .o(wire_n00i_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n00i.width_data = 64,
+ n00i.width_sel = 6;
+ oper_mux n01i
+ (
+ .data({{25{1'b0}}, {17{1'b1}}, {12{1'b0}}, {9{1'b1}}, 1'b0}),
+ .o(wire_n01i_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n01i.width_data = 64,
+ n01i.width_sel = 6;
+ oper_mux n01l
+ (
+ .data({{42{1'b0}}, {21{1'b1}}, 1'b0}),
+ .o(wire_n01l_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n01l.width_data = 64,
+ n01l.width_sel = 6;
+ oper_mux n01O
+ (
+ .data({{63{1'b1}}, 1'b0}),
+ .o(wire_n01O_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n01O.width_data = 64,
+ n01O.width_sel = 6;
+ oper_mux n10i
+ (
+ .data({{7{1'b0}}, {3{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, 1'b0, {3{1'b1}}, {8{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {3{1'b1}}, 1'b0, {3{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, {3{1'b0}}}),
+ .o(wire_n10i_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n10i.width_data = 64,
+ n10i.width_sel = 6;
+ oper_mux n10l
+ (
+ .data({1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {3{1'b1}}, {13{1'b0}}, {3{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, {4{1'b0}}}),
+ .o(wire_n10l_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n10l.width_data = 64,
+ n10l.width_sel = 6;
+ oper_mux n10O
+ (
+ .data({1'b0, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, {3{1'b1}}, {6{1'b0}}}),
+ .o(wire_n10O_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n10O.width_data = 64,
+ n10O.width_sel = 6;
+ oper_mux n11i
+ (
+ .data({{2{1'b1}}, 1'b0, 1'b1, 1'b0, {4{1'b1}}, 1'b0, 1'b1, {4{1'b0}}, 1'b1, {4{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, 1'b1, 1'b0, {10{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, {3{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}}),
+ .o(wire_n11i_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n11i.width_data = 64,
+ n11i.width_sel = 6;
+ oper_mux n11l
+ (
+ .data({{2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, {6{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {3{1'b1}}, {3{1'b0}}, 1'b1, {3{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {10{1'b0}}}),
+ .o(wire_n11l_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n11l.width_data = 64,
+ n11l.width_sel = 6;
+ oper_mux n11O
+ (
+ .data({{4{1'b0}}, {3{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, {6{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, {5{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, {4{1'b0}}, 1'b1, {2{1'b0}}}),
+ .o(wire_n11O_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n11O.width_data = 64,
+ n11O.width_sel = 6;
+ oper_mux n1ii
+ (
+ .data({{3{1'b0}}, {4{1'b1}}, {3{1'b0}}, {4{1'b1}}, {3{1'b0}}, {3{1'b1}}, {2{1'b0}}, {3{1'b1}}, {3{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0}),
+ .o(wire_n1ii_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n1ii.width_data = 64,
+ n1ii.width_sel = 6;
+ oper_mux n1il
+ (
+ .data({{7{1'b0}}, {7{1'b1}}, {6{1'b0}}, {5{1'b1}}, {5{1'b0}}, {4{1'b1}}, {4{1'b0}}, {4{1'b1}}, {4{1'b0}}, {3{1'b1}}, {3{1'b0}}, {2{1'b1}}, {3{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0}),
+ .o(wire_n1il_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n1il.width_data = 64,
+ n1il.width_sel = 6;
+ oper_mux n1OO
+ (
+ .data({{14{1'b0}}, {11{1'b1}}, {9{1'b0}}, {8{1'b1}}, {7{1'b0}}, {5{1'b1}}, {5{1'b0}}, {4{1'b1}}, 1'b0}),
+ .o(wire_n1OO_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ n1OO.width_data = 64,
+ n1OO.width_sel = 6;
+ oper_mux niOi
+ (
+ .data({{2{1'b0}}, {3{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, 1'b0, {4{1'b1}}, 1'b0, {2{1'b1}}, {7{1'b0}}, {2{1'b1}}, 1'b0, 1'b1, {6{1'b0}}, {2{1'b1}}, 1'b0, {3{1'b1}}, {6{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {4{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1}),
+ .o(wire_niOi_o),
+ .sel({a[9:4]}));
+ defparam
+ niOi.width_data = 64,
+ niOi.width_sel = 6;
+ oper_mux niOl
+ (
+ .data({1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {5{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {6{1'b1}}, {3{1'b0}}, {2{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, 1'b0, 1'b1}),
+ .o(wire_niOl_o),
+ .sel({a[9:4]}));
+ defparam
+ niOl.width_data = 64,
+ niOl.width_sel = 6;
+ oper_mux niOO
+ (
+ .data({1'b0, {3{1'b1}}, {4{1'b0}}, {3{1'b1}}, {3{1'b0}}, {2{1'b1}}, {3{1'b0}}, {3{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, {4{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1, {2{1'b0}}, {2{1'b1}}, {3{1'b0}}, 1'b1, 1'b0}),
+ .o(wire_niOO_o),
+ .sel({a[9:4]}));
+ defparam
+ niOO.width_data = 64,
+ niOO.width_sel = 6;
+ oper_mux nl0i
+ (
+ .data({1'b1, {37{1'b0}}, {16{1'b1}}, {10{1'b0}}}),
+ .o(wire_nl0i_o),
+ .sel({a[9:4]}));
+ defparam
+ nl0i.width_data = 64,
+ nl0i.width_sel = 6;
+ oper_mux nl0l
+ (
+ .data({{19{1'b1}}, {13{1'b0}}}),
+ .o(wire_nl0l_o),
+ .sel({a[9:5]}));
+ defparam
+ nl0l.width_data = 32,
+ nl0l.width_sel = 5;
+ oper_mux nl0O
+ (
+ .data({{2{1'b1}}, nill, 1'b0}),
+ .o(wire_nl0O_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nl0O.width_data = 4,
+ nl0O.width_sel = 2;
+ oper_mux nl1i
+ (
+ .data({1'b0, {7{1'b1}}, {6{1'b0}}, {5{1'b1}}, {5{1'b0}}, {4{1'b1}}, {3{1'b0}}, {4{1'b1}}, {3{1'b0}}, {3{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0}),
+ .o(wire_nl1i_o),
+ .sel({a[9:4]}));
+ defparam
+ nl1i.width_data = 64,
+ nl1i.width_sel = 6;
+ oper_mux nl1l
+ (
+ .data({1'b0, {13{1'b1}}, {10{1'b0}}, {7{1'b1}}, {7{1'b0}}, {5{1'b1}}, {4{1'b0}}, {4{1'b1}}, {3{1'b0}}, {3{1'b1}}, {3{1'b0}}, {2{1'b1}}, {2{1'b0}}}),
+ .o(wire_nl1l_o),
+ .sel({a[9:4]}));
+ defparam
+ nl1l.width_data = 64,
+ nl1l.width_sel = 6;
+ oper_mux nl1O
+ (
+ .data({1'b0, {23{1'b1}}, {14{1'b0}}, {9{1'b1}}, {7{1'b0}}, {6{1'b1}}, {4{1'b0}}}),
+ .o(wire_nl1O_o),
+ .sel({a[9:4]}));
+ defparam
+ nl1O.width_data = 64,
+ nl1O.width_sel = 6;
+ oper_mux nlii
+ (
+ .data({{2{1'b1}}, n1l, 1'b0}),
+ .o(wire_nlii_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nlii.width_data = 4,
+ nlii.width_sel = 2;
+ oper_mux nlil
+ (
+ .data({{2{1'b1}}, n1O, 1'b0}),
+ .o(wire_nlil_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nlil.width_data = 4,
+ nlil.width_sel = 2;
+ oper_mux nlilO
+ (
+ .data({1'b1, 1'b0, wire_nllii_dataout, 1'b0}),
+ .o(wire_nlilO_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nlilO.width_data = 4,
+ nlilO.width_sel = 2;
+ oper_mux nliO
+ (
+ .data({{2{1'b1}}, n0i, 1'b0}),
+ .o(wire_nliO_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nliO.width_data = 4,
+ nliO.width_sel = 2;
+ oper_mux nliOi
+ (
+ .data({{2{1'b0}}, wire_nllil_dataout, 1'b0}),
+ .o(wire_nliOi_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nliOi.width_data = 4,
+ nliOi.width_sel = 2;
+ oper_mux nliOl
+ (
+ .data({{2{1'b0}}, wire_nlliO_dataout, 1'b0}),
+ .o(wire_nliOl_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nliOl.width_data = 4,
+ nliOl.width_sel = 2;
+ oper_mux nliOO
+ (
+ .data({{2{1'b0}}, wire_nllli_dataout, 1'b0}),
+ .o(wire_nliOO_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nliOO.width_data = 4,
+ nliOO.width_sel = 2;
+ oper_mux nll0i
+ (
+ .data({{2{1'b0}}, wire_nllOl_dataout, 1'b0}),
+ .o(wire_nll0i_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nll0i.width_data = 4,
+ nll0i.width_sel = 2;
+ oper_mux nll0l
+ (
+ .data({{2{1'b0}}, wire_nllOO_dataout, 1'b0}),
+ .o(wire_nll0l_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nll0l.width_data = 4,
+ nll0l.width_sel = 2;
+ oper_mux nll0O
+ (
+ .data({{2{1'b0}}, wire_nlO1i_dataout, 1'b0}),
+ .o(wire_nll0O_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nll0O.width_data = 4,
+ nll0O.width_sel = 2;
+ oper_mux nll1i
+ (
+ .data({{2{1'b0}}, wire_nllll_dataout, 1'b0}),
+ .o(wire_nll1i_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nll1i.width_data = 4,
+ nll1i.width_sel = 2;
+ oper_mux nll1l
+ (
+ .data({{2{1'b0}}, wire_nlllO_dataout, 1'b0}),
+ .o(wire_nll1l_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nll1l.width_data = 4,
+ nll1l.width_sel = 2;
+ oper_mux nll1O
+ (
+ .data({{2{1'b0}}, wire_nllOi_dataout, 1'b0}),
+ .o(wire_nll1O_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nll1O.width_data = 4,
+ nll1O.width_sel = 2;
+ oper_mux nlli
+ (
+ .data({{2{1'b1}}, n0O, 1'b0}),
+ .o(wire_nlli_o),
+ .sel({wire_nllO_o, wire_nlll_o}));
+ defparam
+ nlli.width_data = 4,
+ nlli.width_sel = 2;
+ oper_mux nlll
+ (
+ .data({{5{1'b1}}, {2{1'b0}}, 1'b1}),
+ .o(wire_nlll_o),
+ .sel({nilii, nilOi, nii0O}));
+ defparam
+ nlll.width_data = 8,
+ nlll.width_sel = 3;
+ oper_mux nllO
+ (
+ .data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}}),
+ .o(wire_nllO_o),
+ .sel({nilii, nilOi, nii0O}));
+ defparam
+ nllO.width_data = 8,
+ nllO.width_sel = 3;
+ oper_mux nlOOl
+ (
+ .data({{2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1, {11{1'b0}}, {7{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {7{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {3{1'b0}}, {2{1'b1}}, 1'b0}),
+ .o(wire_nlOOl_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ nlOOl.width_data = 64,
+ nlOOl.width_sel = 6;
+ oper_mux nlOOO
+ (
+ .data({1'b0, 1'b1, {3{1'b0}}, {12{1'b1}}, {5{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {4{1'b1}}, {3{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {3{1'b1}}, 1'b0}),
+ .o(wire_nlOOO_o),
+ .sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
+ defparam
+ nlOOO.width_data = 64,
+ nlOOO.width_sel = 6;
+ assign
+ nii0i = ((((nil1i & niiOO) & niiOl) & niiOi) & niilO),
+ nii0l = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])),
+ nii0O = (nilOl | nilOO),
+ nii1l = (((((~ nil1i) & (~ niiOO)) & (~ niiOl)) & (~ niiOi)) & (~ niilO)),
+ nii1O = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])),
+ niiii = 1'b1,
+ q = {((~ nilii) & nilil), wire_nlli_o, wire_nliO_o, wire_nlil_o, wire_nlii_o, wire_nl0O_o, wire_nll0O_o, wire_nll0l_o, wire_nll0i_o, wire_nll1O_o, wire_nll1l_o, wire_nll1i_o, wire_nliOO_o, wire_nliOl_o, wire_nliOi_o, wire_nlilO_o};
+endmodule //ip_fp_inv
+//synopsys translate_on
+//VALID FILE
diff --git a/ip/ip_fp_inv_sim/mentor/msim_setup.tcl b/ip/ip_fp_inv_sim/mentor/msim_setup.tcl
new file mode 100644
index 0000000..933eae6
--- /dev/null
+++ b/ip/ip_fp_inv_sim/mentor/msim_setup.tcl
@@ -0,0 +1,272 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_inv
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_inv is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2023.10.31.13:44:11
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_fp_inv"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] {
+ set QUARTUS_INSTALL_DIR "/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
+ set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
+ set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
+ set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] {
+ set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+ echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries/
+ensure_lib ./libraries/work/
+vmap work ./libraries/work/
+vmap work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+ ensure_lib ./libraries/altera_ver/
+ vmap altera_ver ./libraries/altera_ver/
+ ensure_lib ./libraries/lpm_ver/
+ vmap lpm_ver ./libraries/lpm_ver/
+ ensure_lib ./libraries/sgate_ver/
+ vmap sgate_ver ./libraries/sgate_ver/
+ ensure_lib ./libraries/altera_mf_ver/
+ vmap altera_mf_ver ./libraries/altera_mf_ver/
+ ensure_lib ./libraries/altera_lnsim_ver/
+ vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
+ ensure_lib ./libraries/cyclonev_ver/
+ vmap cyclonev_ver ./libraries/cyclonev_ver/
+ ensure_lib ./libraries/cyclonev_hssi_ver/
+ vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
+ ensure_lib ./libraries/cyclonev_pcie_hip_ver/
+ vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
+}
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+ }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_inv.vo"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -voptargs=+acc option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -voptargs=+acc
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "file_copy -- Copy ROM/RAM files to simulation directory"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo " For most designs, this should be overridden"
+ echo " to enable the elab/elab_debug aliases."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
+ echo
+ echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
+ echo
+ echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
+ echo
+ echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
diff --git a/ip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh b/ip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh
new file mode 100755
index 0000000..a2444b0
--- /dev/null
+++ b/ip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh
@@ -0,0 +1,152 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2023.10.31.13:44:11
+
+# ----------------------------------------
+# vcs - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_inv
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, follow the guidelines below.
+#
+# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
+# below into a new file, e.g. named "vcs_sim.sh".
+#
+# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
+# a separate file, e.g. named "filelist.f".
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
+# # set the top-level simulation or testbench module/entity name.
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# # Source the Quartus-generated IP simulation script and do the following:
+# # - Compile the Quartus EDA simulation library and IP simulation files.
+# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
+# # - Compile the design and top-level simulation module/entity using
+# # information specified in "filelist.f".
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# # - Run the simulation.
+# #
+# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
+# TOP_LEVEL_NAME=<simulation top> \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# ----------------------------------------
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the Quartus-generated IP simulation script)
+# #
+# +systemverilogext+.sv
+# <design and testbench files, compile-time options, elaboration options>
+# #
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_inv is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2023.10.31.13:44:11
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_fp_inv"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
+ $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
+ $QSYS_SIMDIR/ip_fp_inv.vo \
+ -top $TOP_LEVEL_NAME
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi
diff --git a/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup b/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup
new file mode 100644
index 0000000..5ae9b46
--- /dev/null
+++ b/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup
@@ -0,0 +1,13 @@
+
+WORK > DEFAULT
+DEFAULT: ./libraries/work/
+work: ./libraries/work/
+altera_ver: ./libraries/altera_ver/
+lpm_ver: ./libraries/lpm_ver/
+sgate_ver: ./libraries/sgate_ver/
+altera_mf_ver: ./libraries/altera_mf_ver/
+altera_lnsim_ver: ./libraries/altera_lnsim_ver/
+cyclonev_ver: ./libraries/cyclonev_ver/
+cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/
+cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
+LIBRARY_SCAN = TRUE
diff --git a/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh
new file mode 100755
index 0000000..f644e44
--- /dev/null
+++ b/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh
@@ -0,0 +1,195 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2023.10.31.13:44:11
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_inv
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_inv is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2023.10.31.13:44:11
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_fp_inv"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_inv.vo"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi
diff --git a/rtl/gfx/fp_add.sv b/rtl/gfx/fp_add.sv
index e8e0c5f..b49a8aa 100644
--- a/rtl/gfx/fp_add.sv
+++ b/rtl/gfx/fp_add.sv
@@ -23,7 +23,7 @@ module fp_add
integer i;
- always @(posedge clk)
+ always_ff @(posedge clk)
if (!stall) begin
a_pipeline[0] <= a;
b_pipeline[0] <= b;
diff --git a/rtl/gfx/fp_inv.sv b/rtl/gfx/fp_inv.sv
new file mode 100644
index 0000000..d2bebdc
--- /dev/null
+++ b/rtl/gfx/fp_inv.sv
@@ -0,0 +1,36 @@
+`include "gfx/gfx_defs.sv"
+
+module fp_inv
+(
+ input logic clk,
+
+ input fp a,
+ input logic stall,
+
+ output fp q
+);
+
+`ifndef VERILATOR
+ ip_fp_inv ip_inv
+ (
+ .en(!stall),
+ .areset(0),
+ .*
+ );
+`else
+ fp pipeline[`FP_INV_STAGES - 1];
+
+ integer i;
+
+ always_ff @(posedge clk)
+ if (!stall) begin
+ pipeline[0] <= a;
+
+ for (i = 1; i < `FP_INV_STAGES - 1; ++i)
+ pipeline[i] <= pipeline[i - 1];
+
+ q <= $c("taller::fp_inv(", pipeline[`FP_INV_STAGES - 2], ")");
+ end
+`endif
+
+endmodule
diff --git a/rtl/gfx/fp_mul.sv b/rtl/gfx/fp_mul.sv
index af5e09c..fda4de2 100644
--- a/rtl/gfx/fp_mul.sv
+++ b/rtl/gfx/fp_mul.sv
@@ -23,7 +23,7 @@ module fp_mul
integer i;
- always @(posedge clk)
+ always_ff @(posedge clk)
if (!stall) begin
a_pipeline[0] <= a;
b_pipeline[0] <= b;
diff --git a/rtl/gfx/gfx_defs.sv b/rtl/gfx/gfx_defs.sv
index 01b7116..1fe0df2 100644
--- a/rtl/gfx/gfx_defs.sv
+++ b/rtl/gfx/gfx_defs.sv
@@ -9,6 +9,7 @@
// Target de 200MHz (reloj es 143MHz) con float16, rounding aproximado
`define FP_ADD_STAGES 10 // ~401 LUTs
`define FP_MUL_STAGES 5 // ~144 LUTs ~1 bloque DSP
+`define FP_INV_STAGES 3 // ~178 LUTs ~1 bloque DSP
typedef logic[`FLOAT_BITS - 1:0] fp;
typedef fp vec2[2];
diff --git a/tb/verilator.hpp b/tb/verilator.hpp
index ff2e9c0..d1d78ff 100644
--- a/tb/verilator.hpp
+++ b/tb/verilator.hpp
@@ -30,6 +30,15 @@ namespace taller
q_bits.fp16 = a_bits.fp16 * b_bits.fp16;
return q_bits.u16;
}
+
+ static inline std::uint16_t fp_inv(std::uint16_t a) noexcept
+ {
+ fp16_bits a_bits, q_bits;
+ a_bits.u16 = a;
+
+ q_bits.fp16 = 1 / a_bits.fp16;
+ return q_bits.u16;
+ }
}
#endif
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