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| author | Alejandro Soto <alejandro@34project.org> | 2023-09-29 22:06:31 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-09-29 22:06:31 -0600 |
| commit | 1c9c08d72f32265501f1f14ad8a0d1e0b2b8850f (patch) | |
| tree | 38664a488deb3dcbf14eab1cd13c9ab4ffa8c29b | |
| parent | bc98bc905c2e796f0d587719196f7e4bf344510a (diff) | |
platform: match SDRAM bandwidth with cache line width
| -rw-r--r-- | platform.qsys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/platform.qsys b/platform.qsys index d8ed205..b66adb2 100644 --- a/platform.qsys +++ b/platform.qsys @@ -490,7 +490,7 @@ <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" /> <parameter name="F2SCLK_WARMRST_Enable" value="false" /> <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter> - <parameter name="F2SDRAM_Width" value="256" /> + <parameter name="F2SDRAM_Width" value="128" /> <parameter name="F2SINTERRUPT_Enable" value="false" /> <parameter name="F2S_Width" value="0" /> <parameter name="FIX_READ_LATENCY" value="8" /> |