From 1c9c08d72f32265501f1f14ad8a0d1e0b2b8850f Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Fri, 29 Sep 2023 22:06:31 -0600
Subject: platform: match SDRAM bandwidth with cache line width

---
 platform.qsys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/platform.qsys b/platform.qsys
index d8ed205..b66adb2 100644
--- a/platform.qsys
+++ b/platform.qsys
@@ -490,7 +490,7 @@
   <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
   <parameter name="F2SCLK_WARMRST_Enable" value="false" />
   <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter>
-  <parameter name="F2SDRAM_Width" value="256" />
+  <parameter name="F2SDRAM_Width" value="128" />
   <parameter name="F2SINTERRUPT_Enable" value="false" />
   <parameter name="F2S_Width" value="0" />
   <parameter name="FIX_READ_LATENCY" value="8" />
-- 
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