blob: b173c4176a5675be3dc87ee53eb88386addce6bd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
|
#include <cstdio>
#include <verilated.h>
#include <verilated_vcd_c.h>
#include "Vhps_sdram_test.h"
#include "Vhps_sdram_test_hps_sdram_test.h"
#include "Vhps_sdram_test_platform.h"
#include "../avalon.hpp"
#include "../mem.hpp"
int main(int argc, char **argv)
{
using namespace taller::avalon;
Verilated::commandArgs(argc, argv);
Vhps_sdram_test top;
#ifdef TRACE
Verilated::traceEverOn(true);
VerilatedVcdC trace;
top.trace(&trace, 0);
trace.open("trace.vcd");
#endif
interconnect<Vhps_sdram_test_platform> avl(*top.hps_sdram_test->plat);
mem hps_ddr3(0x0000'0000, 512 << 20);
avl.attach(hps_ddr3);
int time = 0;
top.clk_clk = 1;
auto tick = [&]()
{
top.clk_clk = !top.clk_clk;
top.eval();
avl.tick(top.clk_clk);
#ifdef TRACE
trace.dump(time++);
#endif
};
auto cycle = [&]()
{
tick();
tick();
std::printf("[%02d] out=0x%02x, done=%d\n", time, top.out, top.done);
};
auto io = [&]()
{
top.io = 0;
cycle();
top.io = 1;
for(int i = 0; i < 4; ++i)
{
cycle();
}
};
top.dir = 1;
top.io = 1;
top.mov = 1;
top.clr = 1;
for(int i = 0; i < 5; ++i)
{
top.add = 0;
cycle();
top.add = 1;
cycle();
}
io();
top.clr = 0;
cycle();
top.clr = 1;
cycle();
top.dir = 0;
io();
#ifdef TRACE
trace.close();
#endif
top.final();
}
|
