strex.py « sim « tb - conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

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path: root/tb/sim/strex.py

blob: d53c3553708786b30093240d377f5cbc8974b3eb (plain)

mem_dumps = [range(0x1000, 0x1008)]

def final():
    assert_reg(r2, 1)
    assert_reg(r5, 1)
    assert_reg(r6, 0)

    assert_mem(0x1000, 0xfedcba98)
    assert_mem(0x1004, 0x01234567)