sdram.py « sim « tb - conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

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path: root/tb/sim/sdram.py

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START = 0x0000_1004
END   = 0x0000_2000

cycles = 30000
mem_dumps = [range(START, END)]

def final():
    assert_mem(START, list(range(42, 42 + (END - START) >> 2)))