tb/sim/modeswitch.py


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def final():
    assert_reg(r0, 0x0000_01d3)
    assert_reg(r1, 0x0000_01d3)
    assert_reg(r2, 0x0000_01d3)
    assert_reg(r3, 0x0000_0090)
    assert_reg(r4, 0x0000_0190)
    assert_reg(r5, 0x6000_0190)
    assert_reg(cpsr, 0x0000_0190)
    assert_reg(r13_svc, 0x2000_0000)
    assert_reg(r13_usr, 0x2000_0000)
    assert_reg(r12_usr, 0xfee1_dead)
    assert_reg(r13_und, 0x0000_01db)