hazards.py « sim « tb - conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

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path: root/tb/sim/hazards.py

blob: b89b15b6bc20b0b0ebc6dfc97e1a04fe300dd6fd (plain)

SP = 256

cycles = 256
mem_dumps = [range(SP - 4, SP)]

def final():
    assert_reg(r0, 59)
    assert_reg(r1, 0)
    assert_reg(sp_svc, SP)
    assert_mem(SP - 4, 3)