blob: f50ed2fcedc8c0517624c16bef7bcd29c33a76f1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
module mp_pe
#(parameter IS_BSP=0)
(
input logic clk,
rst_n,
input logic write,
input logic[7:0] writedata,
output logic[7:0] readdata,
input logic cpu_halted,
breakpoint,
output logic halt,
step
);
struct packed
{
logic step, halt, run;
} req;
struct packed
{
logic breakpoint, cpu_halted;
} status;
assign req = writedata[$bits(req) - 1:0];
assign readdata = {{(8 - $bits(status)){1'b0}}, status};
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
halt <= IS_BSP ? 0 : 1; // Boot es single-core
step <= 0;
status <= {($bits(status)){1'b0}};
end else begin
status.breakpoint <= breakpoint;
status.cpu_halted <= cpu_halted;
//Se hace halt hasta el siguiente ciclo después de que se
//solicita el breakpoint
step <= !breakpoint || (req.step && write);
halt <= (halt || breakpoint || (req.halt && write))
&& !((req.run || req.step) && write);
end
endmodule
|
