rtl/if_common/if_beats.sv


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

interface if_beats
#(int WIDTH = 32);

	logic[WIDTH - 1:0] data;
	logic              ready;
	logic              valid;

	modport tx
	(
		input  ready,
		output data,
		       valid
	);

	modport rx
	(
		input  data,
		       valid,
		output ready
	);

	modport peek
	(
		input  data,
		       ready,
		       valid
	);

endinterface