summaryrefslogtreecommitdiff
path: root/rtl/gfx/gfx_regfile_io.sv
blob: 24590497131aedc8583a20beeb763e18c66b87fd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
interface gfx_regfile_io;

	import gfx::*;

	struct
	{
		group_id    group;
		sgpr_num    a_sgpr,
		            b_sgpr;
		vgpr_num    a_vgpr,
		            b_vgpr;
		logic[12:0] b_imm;
		logic       a_scalar,
		            b_scalar,
		            b_is_imm,
		            b_is_const,
		            scalar_rev;
	} op;

	struct
	{
		logic    write;
		group_id group;
		sgpr_num sgpr;
		word     data;
	} sgpr_write;

	struct
	{
		lane_mask mask;
		group_id  group;
		vgpr_num  vgpr;
		word      data[SHADER_LANES];
	} vgpr_write;

	word a[SHADER_LANES], b[SHADER_LANES], sgpr_write_data, vgpr_write_data[SHADER_LANES];
	logic mask_wb_write, pc_wb_write;
	word_ptr pc_back, pc_front, pc_wb;
	group_id mask_back_group, mask_wb_group, pc_back_group, pc_front_group, pc_wb_group;
	lane_mask mask_back, mask_wb;

	modport ab
	(
		input  a,
		       b
	);

	modport read
	(
		output op
	);

	modport bind_
	(
		input  pc_front,

		output pc_front_group
	);

	modport wb
	(
		input  pc_back,
		       mask_back,

		output sgpr_write,
		       vgpr_write,

		       pc_back_group,
		       mask_back_group,

		       pc_wb,
		       pc_wb_group,
		       pc_wb_write,

		       mask_wb,
		       mask_wb_group,
		       mask_wb_write
	);

	modport regs
	(
		input  op,
		       sgpr_write,
		       vgpr_write,

		       pc_back_group,
		       pc_front_group,
		       mask_back_group,

		       pc_wb,
		       pc_wb_group,
		       pc_wb_write,

		       mask_wb,
		       mask_wb_group,
		       mask_wb_write,

		output a,
		       b,

		       pc_back,
		       pc_front,
		       mask_back
	);

endinterface