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// verilator lint_off WIDTHEXPAND
// verilator lint_off WIDTHTRUNC
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:34:54 2011
//--
//-- Source file: dma_ch.v
//---------------------------------------------------------
module dma_axi32_core0_ch_empty (clk,reset,scan_en,pclk,clken,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,rd_cmd_split,rd_cmd_line,rd_clr_line,rd_clr,rd_clr_load,rd_slverr,rd_decerr,wr_cmd_split,wr_cmd_pending,wr_clr_line,wr_clr,wr_clr_last,wr_slverr,wr_decerr,load_wr,load_wr_cycle,load_wdata,load_req_in_prog,int_all_proc,ch_start,idle,ch_active,ch_rd_active,ch_wr_active,wr_last_cmd,rd_line_cmd,wr_line_cmd,rd_go_next_line,wr_go_next_line,rd_ready,rd_burst_start,rd_burst_addr,rd_burst_size,rd_tokens,rd_port_num,rd_periph_delay,rd_clr_valid,rd_transfer,rd_transfer_size,rd_clr_stall,wr_ready,wr_burst_start,wr_burst_addr,wr_burst_size,wr_tokens,wr_port_num,wr_periph_delay,wr_clr_valid,wr_transfer,wr_transfer_size,wr_next_size,wr_clr_stall,wr_incr,timeout_aw,timeout_w,timeout_ar,wdt_timeout,fifo_wr,fifo_wdata,fifo_wsize,fifo_rd,fifo_rsize,fifo_rd_valid,fifo_rdata,fifo_wr_ready,joint_mode,joint_remote,rd_page_cross,wr_page_cross,joint_in_prog,joint_not_in_prog,joint_mux_in_prog,joint_req);
input clk;
input reset;
input scan_en;
input pclk;
input clken;
input pclken;
input psel;
input penable;
input [7:0] paddr;
input pwrite;
input [31:0] pwdata;
output [31:0] prdata;
output pslverr;
input [31:1] periph_tx_req;
output [31:1] periph_tx_clr;
input [31:1] periph_rx_req;
output [31:1] periph_rx_clr;
input rd_cmd_split;
input rd_cmd_line;
input rd_clr_line;
input rd_clr;
input rd_clr_load;
input rd_slverr;
input rd_decerr;
input wr_cmd_split;
input wr_cmd_pending;
input wr_clr_line;
input wr_clr;
input wr_clr_last;
input wr_slverr;
input wr_decerr;
input load_wr;
input [1:0] load_wr_cycle;
input [32-1:0] load_wdata;
output load_req_in_prog;
output [1-1:0] int_all_proc;
input ch_start;
output idle;
output ch_active;
output ch_rd_active;
output ch_wr_active;
output wr_last_cmd;
output rd_line_cmd;
output wr_line_cmd;
output rd_go_next_line;
output wr_go_next_line;
output rd_ready;
input rd_burst_start;
output [32-1:0] rd_burst_addr;
output [7-1:0] rd_burst_size;
output [`TOKEN_BITS-1:0] rd_tokens;
output rd_port_num;
output [`DELAY_BITS-1:0] rd_periph_delay;
output rd_clr_valid;
input rd_transfer;
input [3-1:0] rd_transfer_size;
output rd_clr_stall;
output wr_ready;
input wr_burst_start;
output [32-1:0] wr_burst_addr;
output [7-1:0] wr_burst_size;
output [`TOKEN_BITS-1:0] wr_tokens;
output wr_port_num;
output [`DELAY_BITS-1:0] wr_periph_delay;
output wr_clr_valid;
input wr_transfer;
input [3-1:0] wr_transfer_size;
input [3-1:0] wr_next_size;
output wr_clr_stall;
output wr_incr;
input timeout_aw;
input timeout_w;
input timeout_ar;
input wdt_timeout;
input fifo_wr;
input [32-1:0] fifo_wdata;
input [3-1:0] fifo_wsize;
input fifo_rd;
input [3-1:0] fifo_rsize;
output fifo_rd_valid;
output [32-1:0] fifo_rdata;
output fifo_wr_ready;
input joint_mode;
input joint_remote;
input rd_page_cross;
input wr_page_cross;
output joint_in_prog;
output joint_not_in_prog;
output joint_mux_in_prog;
output joint_req;
assign prdata = 'd0;
assign pslverr = 'd1; //return error
assign periph_tx_clr = 'd0;
assign periph_rx_clr = 'd0;
assign load_req_in_prog = 'd0;
assign int_all_proc = 'd0;
assign idle = 'd1;
assign ch_active = 'd0;
assign ch_rd_active = 'd0;
assign ch_wr_active = 'd0;
assign wr_last_cmd = 'd0;
assign rd_line_cmd = 'd0;
assign wr_line_cmd = 'd0;
assign rd_go_next_line = 'd0;
assign wr_go_next_line = 'd0;
assign rd_ready = 'd0;
assign rd_burst_addr = 'd0;
assign rd_burst_size = 'd0;
assign rd_tokens = 'd0;
assign rd_port_num = 'd0;
assign rd_periph_delay = 'd0;
assign rd_clr_valid = 'd0;
assign rd_clr_stall = 'd0;
assign wr_ready = 'd0;
assign wr_burst_addr = 'd0;
assign wr_burst_size = 'd0;
assign wr_tokens = 'd0;
assign wr_port_num = 'd0;
assign wr_periph_delay = 'd0;
assign wr_clr_valid = 'd0;
assign wr_clr_stall = 'd0;
assign wr_incr = 'd0;
assign fifo_rd_valid = 'd0;
assign fifo_rdata = 'd0;
assign fifo_wr_ready = 'd0;
assign joint_in_prog = 'd0;
assign joint_not_in_prog = 'd0;
assign joint_mux_in_prog = 'd0;
assign joint_req = 'd0;
endmodule
// verilator lint_on WIDTHEXPAND
// verilator lint_on WIDTHTRUNC
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