blob: 0453cad41e789877a573db6fd43cbb3cbd65a96e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
module core_mul_mul
#(parameter W=32)
(
input logic[W - 1:0] a,
b,
input logic clk,
output logic[(W*2) - 1:0] q,
output logic z,
n
);
logic[(W*2):0] booth;
logic[1:0] Q;
logic[W-1:0] A, B;
logic[W - 1:0] counter;
initial begin
booth = { W{1'b0}, b, 0 }
Q = booth[1:0];
A = booth[(W*2):W];
B = a;
counter = W;
end
always@(posedge clk or negedge rst_n) begin
if (~rst_n) begin
booth = { W{1'b0}, b, 0 }
Q = booth[1:0];
//A = booth[(W*2):W];
//B = a;
counter = W;
end
else begin
A = booth[(W*2):W];
unique case(Q)
2'b01:
booth[(W*2):W] = A + B;
2'b10:
booth[(W*2):W] = A - B;
// 2'b11 o 2'b00:
default: ;
endcase
booth >>> 1;
counter = counter - 1;
end
always_comb
if(counter == 0) begin
q = booth[(W*2):1]
end
end
endmodule
|
